[PATCH v5 00/21] Enable drm/imagination BXM-4-64 Support for LicheePi 4A

Michal Wilczynski
2025-02-19T14:02:52Z

The LicheePi 4A board, featuring the T-HEAD TH1520 SoC, includes an Imagination
Technologies BXM-4-64 GPU. Initial support for this GPU was provided through a
downstream driver [1]. Recently, efforts have been made to upstream support for
the Rogue family GPUs, which the BXM-4-64 is part of [2].

While the initial upstream driver focused on the AXE-1-16 GPU, newer patches
have introduced support for the BXS-4-64 GPU [3]. The modern upstream
drm/imagination driver is expected to support the BXM-4-64 as well [4][5]. As
this support is being developed, it's crucial to upstream the necessary glue
code including clock and power-domain drivers so they're ready for integration
with the drm/imagination driver.

Recent Progress:

Firmware Improvements:
Since August, the vendor has provided updated firmware
[6][7] that correctly initiates the firmware for the BXM-4-64.

Mesa Driver Testing:
The vendor-supplied Mesa driver [8] partially works with Vulkan examples, such
as rendering a triangle using Sascha Willems' Vulkan samples [9]. Although the
triangle isn't rendered correctly (only the blue background appears), shader
job submissions function properly, and IOCTL calls are correctly invoked. For
testing, we used the following resources:

Kernel Source: Custom kernel with necessary modifications [10].
Mesa Driver: Vendor-provided Mesa implementation [11].

Dependencies:
Testing required a functional Display Processing Unit (DPU) and HDMI driver,
which are currently not upstreamed. Efforts are underway to upstream the DPU
DC8200 driver used in StarFive boards [12], which is the same DPU used on the
LicheePi 4A. Once the DPU and HDMI drivers are upstreamed, GPU support can be
fully upstream.

Testing Status:
This series has been tested by performing a probe-only operation, confirming
that the firmware begins execution. The probe function initiates firmware
execution and waits for the firmware to flip a specific status bit.

[ 12.637880] powervr ffef400000.gpu: [drm] loaded firmware powervr/rogue_36.52.104.182_v1.fw
[ 12.648979] powervr ffef400000.gpu: [drm] FW version v1.0 (build 6645434 OS)
[ 12.678906] [drm] Initialized powervr 1.0.0 for ffef400000.gpu on minor 0

Power Management:
Full power management capabilities require implementing the T-HEAD SoC AON
protocol messaging via the hardware mailbox. Support for the mailbox was merged
in kernel 6.13 [13], and the AON protocol implementation is part of this
series, since v2. Therefore this series support full power management
capabilities for the GPU driver.

Thanks everyone for taking the time to review the last revision ! Your
guidance and the direction was very helpful.

v5:

Reset Changes:
- Moved the reset de-assertion from the reset driver to the clock driver. The
reset is now only de-asserted once the sys and core clocks have been enabled
- Added and exported the GPU_CLKGEN reset, allowing the clock driver to reset
the GPU clock circuit

Clock Changes:
- Introduced a new macro CCU_GATE_CLK_OPS, which allows providing custom clk_ops.
In the case of the 'MEM' clock, it provides empty clk_nops. Later, this clock
is provided to the GPU node, thereby avoiding any ABI breakage
- Used the CCU_GATE_CLK_OPS macro to implement a workaround for de-asserting
the clkgen reset only after both core and sys clocks are enabled. This
sequence is required to properly initialize the GPU

Power-domain/Firmware Changes:
- Changed the AON driver to be a set of library functions rather than a
standalone driver

Imagination Driver Changes:
- Moved the recommended 1 microsecond delay after de-asserting GPU reset to the
Imagination driver itself
- Included the mem clock to preserve the ABI, acknowledging that this clock
exists but is not configurable from the SoC
- A few remaining conflicts will be resolved after the dt-binding changes
mentioned in the review are merged

v4:

Device Tree Changes:
- restructured power device tree bindings by abstracting power-domain IDs from
firmware IDs, with the mappings now defined in a dedicated header file
- retained existing clock-names in img,powervr-rogue.yaml to maintain ABI
compatibility, despite having only one downstream user
- enhanced documentation for new Video Output (VO) clock inputs in device tree
bindings

Reset Driver Changes:
- reverted reset-cells configuration to single cell as in v2
- maintained reset definitions in device tree bindings while deferring
implementation of watchdog timer (WDT) reset functionality
- addressed implementation issues in the DRM/Imagination reset driver

Power Domain Changes:
- added workaround to disable AUDIO power domain to prevent firmware crashes

v3:

Device Tree Changes:
- consolidated device tree representation by merging aon and power-domain nodes
while maintaining separate drivers internally
- power-domain driver is now instantiated from within the aon driver
- updated img,powervr-rogue.yaml to use allOf and oneOf for better schema
organization

AP Clock Driver Improvements:
- reworked driver to support multiple clock controllers through .compatible
and .data instead of using multiple address spaces in dt-binding. This change
allows to re-use the driver code for multiple clock controllers

Code Quality and Documentation:
- fixed optional module dependencies in Kconfig
- added kernel-doc comments for all exported functions
- implemented th1520_aon_remove() to properly clean up mailbox channel
resources
- removed unnecessary of.h header in multiple drivers
- refactored reset driver to use zero cells

v2:

Removed AP_SUBSYS clock refactoring commits (1-6):
- instead of refactoring, I opted to extend the current driver and its
associated device tree node to include support for a second address space.

Expanded patchset scope to fully support power management capabilities:
- introduced a new firmware driver to manage power-related operations.
- rewrote the power-domain driver to function alongside the firmware driver.
These nodes in the device tree lack direct address spaces, despite
representing HW blocks. Control is achieved via firmware protocol messages
transmitted through a mailbox to the E902 core.

Implemented a reset controller for the TH1520 SoC:
- developed a reset controller driver for the TH1520 to manage reset
sequences.
- updated the drm/imagination driver to act as a reset controller consumer.
While this patchset is focused on the LPI4A board, the reset controller is
designed to be useful for other boards, such as the BPI-3F, which also require
a reset sequence after power-up.

Updated dt-bindings:
- added new dt-bindings for power, reset, and firmware nodes.
- updated the powervr dt-binding to include reset support and new compatibles.
- ran dtbs_check and dt_binding_check to ensure compliance.

Addressed code quality:
- resolved all checkpatch issues using --strict, except for the call to
devm_clk_hw_register_gate_parent_data(). The current implementation remains
preferable in this context, and clang-format aligns with this choice.

References:

[1] Downstream Driver Source:
https://gitlab.freedesktop.org/frankbinns/powervr/-/blob/cb1929932095649a24f051b9cfdd2cd2ceab35cb/drivers/gpu/drm/img-rogue/Kconfig

[2] Initial Upstream Driver Series:
https://lore.kernel.org/all/cover.1700668843.git.donald.robson@imgtec.com/

[3] BXS-4-64 GPU Support Patches:
https://lore.kernel.org/all/20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865892@imgtec.com/

[4] Firmware Issue Discussion 1:
https://gitlab.freedesktop.org/imagination/linux-firmware/-/issues/1

[5] Firmware Issue Discussion 2:
https://gitlab.freedesktop.org/imagination/linux-firmware/-/issues/2

[6] Firmware Update Commit 1:
https://gitlab.freedesktop.org/imagination/linux-firmware/-/commit/6ac2247e9a1d1837af495fb6d0fbd6f35547c2d1

[7] Firmware Update Commit 2:
https://gitlab.freedesktop.org/imagination/linux-firmware/-/commit/efbebc90f25adb2b2e1499e3cc24ea3f3c3e4f4c

[8] Vendor-Provided Mesa Driver:
https://gitlab.freedesktop.org/imagination/mesa/-/tree/dev/devinfo

[9] Sascha Willems' Vulkan Samples:     https://github.com/SaschaWillems/Vulkan

[10] Test Kernel Source:
https://github.com/mwilczy/linux/tree/2_December_reference_linux_kernel_imagination

[11] Test Mesa Driver:
https://github.com/mwilczy/mesa-reference

[12] DPU DC8200 Driver Upstream Attempt:
https://lore.kernel.org/all/20241120061848.196754-1-keith.zhao@starfivetech.com/

[13] Pull request kernel 6.13 for mailbox
https://lore.kernel.org/all/CABb+yY33qnivK-PzqpSMgmtbFid4nS8wcNvP7wED9DXrYAyLKg@mail.gmail.com/

Michal Wilczynski (21):
dt-bindings: clock: thead: Add TH1520 VO clock controller
clk: thead: Add clock support for VO subsystem in T-Head TH1520 SoC
dt-bindings: firmware: thead,th1520: Add support for firmware node
firmware: thead: Add AON firmware protocol driver
dt-bindings: power: Add TH1520 SoC power domains
pmdomain: thead: Add power-domain driver for TH1520
riscv: Enable PM_GENERIC_DOMAINS for T-Head SoCs
clk: thead: Add support for custom ops in CCU_GATE_CLK_OPS macro
dt-bindings: clock: thead: Add GPU clkgen reset property
clk: thead: Add GPU clock gate control with CLKGEN reset support
dt-bindings: reset: Add T-HEAD TH1520 SoC Reset Controller
reset: thead: Add TH1520 reset controller driver
drm/imagination: Add reset controller support for GPU initialization
dt-bindings: gpu: Add 'resets' property for GPU initialization
dt-bindings: gpu: Add support for T-HEAD TH1520 GPU
drm/imagination: Add support for IMG BXM-4-64 GPU
drm/imagination: Enable PowerVR driver for RISC-V
riscv: dts: thead: Add device tree VO clock controller
riscv: dts: thead: Introduce power domain nodes with aon firmware
riscv: dts: thead: Introduce reset controller node
riscv: dts: thead: Add GPU node to TH1520 device tree

.../bindings/clock/thead,th1520-clk-ap.yaml | 33 +-
.../bindings/firmware/thead,th1520-aon.yaml | 53 ++++
.../bindings/gpu/img,powervr-rogue.yaml | 42 ++-
.../bindings/reset/thead,th1520-reset.yaml | 44 +++
MAINTAINERS | 8 +
arch/riscv/Kconfig.socs | 1 +
arch/riscv/boot/dts/thead/th1520.dtsi | 36 +++
drivers/clk/thead/clk-th1520-ap.c | 298 ++++++++++++++++--
drivers/firmware/Kconfig | 9 +
drivers/firmware/Makefile | 1 +
drivers/firmware/thead,th1520-aon.c | 247 +++++++++++++++
drivers/gpu/drm/imagination/Kconfig | 2 +-
drivers/gpu/drm/imagination/pvr_device.c | 21 ++
drivers/gpu/drm/imagination/pvr_device.h | 9 +
drivers/gpu/drm/imagination/pvr_drv.c | 2 +
drivers/gpu/drm/imagination/pvr_power.c | 22 +-
drivers/pmdomain/Kconfig | 1 +
drivers/pmdomain/Makefile | 1 +
drivers/pmdomain/thead/Kconfig | 12 +
drivers/pmdomain/thead/Makefile | 2 +
drivers/pmdomain/thead/th1520-pm-domains.c | 209 ++++++++++++
drivers/reset/Kconfig | 10 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-th1520.c | 141 +++++++++
.../dt-bindings/clock/thead,th1520-clk-ap.h | 34 ++
.../dt-bindings/power/thead,th1520-power.h | 19 ++
.../dt-bindings/reset/thead,th1520-reset.h | 16 +
.../linux/firmware/thead/thead,th1520-aon.h | 200 ++++++++++++
28 files changed, 1437 insertions(+), 37 deletions(-)
create mode 100644 Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml
create mode 100644 Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml
create mode 100644 drivers/firmware/thead,th1520-aon.c
create mode 100644 drivers/pmdomain/thead/Kconfig
create mode 100644 drivers/pmdomain/thead/Makefile
create mode 100644 drivers/pmdomain/thead/th1520-pm-domains.c
create mode 100644 drivers/reset/reset-th1520.c
create mode 100644 include/dt-bindings/power/thead,th1520-power.h
create mode 100644 include/dt-bindings/reset/thead,th1520-reset.h
create mode 100644 include/linux/firmware/thead/thead,th1520-aon.h

--
2.34.1