Re: [PATCH 1/2] clk: sunxi-ng: mp: provide wrapper for setting feature flags

Jernej Škrabec
2025-02-26T16:00:39Z

Dne sreda, 26. februar 2025 ob 11:37:33 Srednjeevropski standardni čas je Andre Przywara napisal(a):
> So far our sunxi clock instantiation macros set the required flags
> depending on the clock type, but the new "dual divider MP clock"
> requires us to pass that piece of information in by the macro user.
>
> Add a new wrapper macro that allows to specify a "features" field, to
> allow marking those dual-divider clocks accordingly.
> Since the MMC clocks will be a prominent user, combine this with the
> postdiv field required there. Users who just want the feature, can
> pass in a postdiv of 1, users of just the postdiv can pass in a feature
> mask of 0.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

I'm fine with the new macro, but we don't need to chain them, especially
since this forces all of them to have post divider.

What about making special, standalone macro for that?

Best regards,
Jernej

> ---
> drivers/clk/sunxi-ng/ccu_mp.h | 19 +++++++++++++++++--
> 1 file changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu_mp.h b/drivers/clk/sunxi-ng/ccu_mp.h
> index 6e50f3728fb5f..1da1dcaf62ea9 100644
> --- a/drivers/clk/sunxi-ng/ccu_mp.h
> +++ b/drivers/clk/sunxi-ng/ccu_mp.h
> @@ -82,18 +82,22 @@ struct ccu_mp {
> _muxshift, _muxwidth, \
> 0, _flags)
>
> -#define SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
> +#define SUNXI_CCU_MP_MUX_GATE_POSTDIV_FEAT(_struct, _name, _parents, _reg, \
> _mshift, _mwidth, \
> _pshift, _pwidth, \
> _muxshift, _muxwidth, \
> - _gate, _flags) \
> + _gate, _postdiv, \
> + _flags, _features) \
> struct ccu_mp _struct = { \
> .enable = _gate, \
> .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
> .p = _SUNXI_CCU_DIV(_pshift, _pwidth), \
> .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
> + .fixed_post_div = _postdiv, \
> .common = { \
> .reg = _reg, \
> + .features = CCU_FEATURE_FIXED_POSTDIV | \
> + _features, \
> .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
> _parents, \
> &ccu_mp_ops, \
> @@ -101,6 +105,17 @@ struct ccu_mp {
> } \
> }
>
> +#define SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
> + _mshift, _mwidth, \
> + _pshift, _pwidth, \
> + _muxshift, _muxwidth, \
> + _gate, _flags) \
> + SUNXI_CCU_MP_MUX_GATE_POSTDIV_FEAT(_struct, _name, _parents, \
> + _reg, _mshift, _mwidth, \
> + _pshift, _pwidth, \
> + _muxshift, _muxwidth, \
> + _gate, 1, _flags, 0)
> +
> #define SUNXI_CCU_MP_DATA_WITH_MUX(_struct, _name, _parents, _reg, \
> _mshift, _mwidth, \
> _pshift, _pwidth, \
>