RE: [PATCH 08/17] drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range

Biju Das
2025-03-31T12:26:24Z

Hi Prabhakar,

Thanks for the patch.

> -----Original Message-----
> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: 30 March 2025 22:07
> Subject: [PATCH 08/17] drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> The VCLK range for Renesas RZ/G2L SoC is 148.5 MHz to 5.803 MHz. Add a minimum clock check in the
> mode_valid callback to ensure that the clock value does not fall below the valid range.
>
> Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Cheers,
Biju

> ---
> drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-
> du/rzg2l_mipi_dsi.c
> index fa7a1ae22aa3..c6f60b7f203b 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> @@ -585,6 +585,9 @@ rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
> if (mode->clock > 148500)
> return MODE_CLOCK_HIGH;
>
> + if (mode->clock < 5803)
> + return MODE_CLOCK_LOW;
> +
> return MODE_OK;
> }
>
> --
> 2.49.0