[PATCH 12/17] drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations

Prabhakar
2025-03-30T21:08:18Z

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve
precision, especially for the RZ/V2H(P) SoC, where PLL dividers require
high accuracy.

These changes prepare the driver for upcoming RZ/V2H(P) SoC support.

Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
index 44b95082b29c..84c3384aa911 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
@@ -31,7 +31,7 @@
struct rzg2l_mipi_dsi;

struct rzg2l_mipi_dsi_hw_info {
- int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long hsfreq);
+ int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long long hsfreq_mhz);
void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi);
u32 phy_reg_offset;
u32 link_reg_offset;
@@ -201,8 +201,9 @@ static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi *dsi, u32 reg)
*/

static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,
- unsigned long hsfreq)
+ unsigned long long hsfreq_mhz)
{
+ unsigned long hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_mhz, KILO);
const struct rzg2l_mipi_dsi_timings *dphy_timings;
unsigned int i;
u32 dphyctrl0;
@@ -275,6 +276,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
const struct drm_display_mode *mode)
{
unsigned long hsfreq, vclk_rate;
+ unsigned long long hsfreq_mhz;
unsigned int bpp;
u32 txsetr;
u32 clstptsetr;
@@ -303,9 +305,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
*/
bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
vclk_rate = clk_get_rate(dsi->vclk);
- hsfreq = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp, dsi->lanes);
+ hsfreq_mhz = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp * KILO * 1ULL, dsi->lanes);

- ret = dsi->info->dphy_init(dsi, hsfreq);
+ ret = dsi->info->dphy_init(dsi, hsfreq_mhz);
if (ret < 0)
goto err_phy;

@@ -313,6 +315,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
txsetr = TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN;
rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr);

+ hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_mhz, KILO);
/*
* Global timings characteristic depends on high speed Clock Frequency
* Currently MIPI DSI-IF just supports maximum FHD@60 with:
@@ -780,7 +783,7 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
* mode->clock and format are not available. So initialize DPHY with
* timing parameters for 80Mbps.
*/
- ret = dsi->info->dphy_init(dsi, 80000000);
+ ret = dsi->info->dphy_init(dsi, 80000000ULL * KILO);
if (ret < 0)
goto err_phy;

--
2.49.0