[PATCH 14/17] drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for RZ/V2H(P)

Prabhakar
2025-03-30T21:08:22Z

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to
allow additional D-PHY register configurations after enabling data and
clock lanes. This is required for the RZ/V2H(P) SoC but not for the
RZ/G2L SoC.

Modify `rzg2l_mipi_dsi_startup()` to invoke `dphy_late_init` if defined,
ensuring SoC-specific initialization is performed only when necessary.

This change prepares for RZ/V2H(P) SoC support while maintaining
compatibility with existing platforms.

Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
index 0ffef641e2bc..143bb01e6f50 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
@@ -34,6 +34,7 @@ struct rzg2l_mipi_dsi;

struct rzg2l_mipi_dsi_hw_info {
int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long long hsfreq_mhz);
+ void (*dphy_late_init)(struct rzg2l_mipi_dsi *dsi);
void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi);
u32 phy_reg_offset;
u32 link_reg_offset;
@@ -318,6 +319,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
txsetr = TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN;
rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr);

+ if (dsi->info->dphy_late_init)
+ dsi->info->dphy_late_init(dsi);
+
hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_mhz, KILO);
/*
* Global timings characteristic depends on high speed Clock Frequency
--
2.49.0