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[213.67.3.247]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-32a79f698dcsm2594311fa.92.2025.05.28.07.09.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 07:09:20 -0700 (PDT) From: "Edgar E. Iglesias" To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jank@cadence.com Cc: edgar.iglesias@amd.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: clk: fixed-mmio-clock: Add optional ready reg Date: Wed, 28 May 2025 16:09:16 +0200 Message-ID: <20250528140917.876453-2-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250528140917.876453-1-edgar.iglesias@gmail.com> References: <20250528140917.876453-1-edgar.iglesias@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: "Edgar E. Iglesias" Add an optional ready register and properties describing bitfields that signal when the clock is ready. This can for example be useful to describe PLL lock bits. Signed-off-by: Edgar E. Iglesias --- .../bindings/clock/fixed-mmio-clock.yaml | 37 ++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/fixed-mmio-clock.yaml b/Documentation/devicetree/bindings/clock/fixed-mmio-clock.yaml index e22fc272d023..57419b4de343 100644 --- a/Documentation/devicetree/bindings/clock/fixed-mmio-clock.yaml +++ b/Documentation/devicetree/bindings/clock/fixed-mmio-clock.yaml @@ -10,6 +10,11 @@ description: This binding describes a fixed-rate clock for which the frequency can be read from a single 32-bit memory mapped I/O register. + An optional ready register can be specified in a second reg entry. + The ready register will be polled until it signals ready prior to reading + the fixed rate. This is useful for example to optionally wait for a PLL + to lock. + It was designed for test systems, like FPGA, not for complete, finished SoCs. @@ -21,7 +26,10 @@ properties: const: fixed-mmio-clock reg: - maxItems: 1 + minItems: 1 + items: + - description: Fixed rate register + - description: Optional clock ready register "#clock-cells": const: 0 @@ -29,6 +37,24 @@ properties: clock-output-names: maxItems: 1 + ready-timeout-us: + description: + Optional timeout in micro-seconds when polling for clock readiness. + 0 means no timeout. + default: 0 + + ready-mask: + description: + Optional mask to apply when reading the ready register. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0xffffffff + + ready-value: + description: + When a ready register is specified in reg, poll the ready reg until + ready-reg & ready-mask == ready-value. + $ref: /schemas/types.yaml#/definitions/uint32 + required: - compatible - reg @@ -44,4 +70,13 @@ examples: reg = <0xfd020004 0x4>; clock-output-names = "sysclk"; }; + - | + clock@fd040000 { + compatible = "fixed-mmio-clock"; + #clock-cells = <0>; + reg = <0xfd040000 0x4 0xfd040004 0x4>; + ready-mask = <1>; + ready-value = <1>; + clock-output-names = "pclk"; + }; ... -- 2.43.0