From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 651F01A314C; Tue, 10 Jun 2025 01:24:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749518661; cv=none; b=brMIPByr1L0RsLoJYxCAdlaZB1O6fRjYoh19l3Y/RRycuoNd1j2KDFu0c3yXqEorrAlQDwVdkkumuGU67lhcDy4H/Lmhr/5o4plO+CXYJu/DuCWpe3duoq4vGqbpwhRZ4038MMPAm/EhvUcI+I92S7FJ5QnqbqRiZnkpVYhr6VQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749518661; c=relaxed/simple; bh=JFE7d/JvqrWQ8d6qQ7V3lXofuMxZxxI50aY3cxps8NE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FrV1XiNpPKJJxSE4W0z74A+dYcdvNgqNKr0rElHY0mBPDJ7EjQn8xlutXZDbOeOFkfTEmaWGaYweUv9PxGqDSO3k9qT5mmRWfR4Ovea3hKvv4A7cTXpwZcYpyS0RdABuKxpveTddptsZ2Vke06g9/+9qNE1owLNZO18XQJILh1I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 10 Jun 2025 09:24:06 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 10 Jun 2025 09:24:06 +0800 From: Jacky Chou To: , , , CC: , , , , , , , , , , , , , , , Subject: [net-next v2 1/4] dt-bindings: net: ftgmac100: Add resets property Date: Tue, 10 Jun 2025 09:24:03 +0800 Message-ID: <20250610012406.3703769-2-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250610012406.3703769-1-jacky_chou@aspeedtech.com> References: <20250610012406.3703769-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Add optional resets property for Aspeed SoCs to reset the MAC and RGMII/RMII. Signed-off-by: Jacky Chou --- .../bindings/net/faraday,ftgmac100.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml b/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml index 55d6a8379025..8b9688c5b985 100644 --- a/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml +++ b/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml @@ -35,6 +35,11 @@ properties: - description: MAC IP clock - description: RMII RCLK gate for AST2500/2600 + resets: + maxItems: 1 + description: + Optional reset control for the MAC controller + clock-names: minItems: 1 items: @@ -74,6 +79,20 @@ required: - reg - interrupts +allOf: + - if: + properties: + compatible: + contains: + enum: + - aspeed,ast2600-mac + then: + properties: + resets: true + else: + properties: + resets: false + unevaluatedProperties: false examples: -- 2.34.1