From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-oa1-f44.google.com (mail-oa1-f44.google.com [209.85.160.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DE031EFFBB for ; Fri, 13 Jun 2025 01:11:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.44 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749777113; cv=none; b=Kgm3jhNMYGuS+E8YoRnqTQdK9ZitIoBCtt98qXjA9QLoy++Hmh6SurVsCQmV8wVmdkstRwkfCX4WqOlo8quYTiNLa0Qf2Wr51Rg0Y34bLfMykyBMRuVR0VhU9tX24/jr+spg+cpK3A61aS0jiM+R+NSxU2Xtz7VSKyXwgEewdOs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749777113; c=relaxed/simple; bh=Yykr4pXHm+eFZeLoxnQj4YQ7g7m8no0bRdRqTGC2FXA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QZ35IfT44mNtR+H1XugmRorh0IM0ZOkALhRH/g3PfyUVcV8sPVXymEX97fbONMId/R8KdnJXdLpOYsHHEAAVHGJj1t1KZOcUd7+UzFBXjA+GBBERcTg9KqfyjUlTmorcJhi1P0CyEDm4qf6TRYXxuWv2Ndupn7RkMpH0RC1I7D4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riscstar.com; spf=pass smtp.mailfrom=riscstar.com; dkim=pass (2048-bit key) header.d=riscstar-com.20230601.gappssmtp.com header.i=@riscstar-com.20230601.gappssmtp.com header.b=3eCA+l69; arc=none smtp.client-ip=209.85.160.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riscstar.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=riscstar.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=riscstar-com.20230601.gappssmtp.com header.i=@riscstar-com.20230601.gappssmtp.com header.b="3eCA+l69" Received: by mail-oa1-f44.google.com with SMTP id 586e51a60fabf-2ea08399ec8so983895fac.1 for ; Thu, 12 Jun 2025 18:11:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=riscstar-com.20230601.gappssmtp.com; s=20230601; t=1749777110; x=1750381910; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CofZ6mxwdPQ5E5kE6D3I1SRbGpA+t1hpeEYsYL5jGT4=; b=3eCA+l69uHb+cRpG2uge1Mua1V3U2/ZmneraB7uuLbWmFTwiUtodDkmxBv11PrFPVc 6XwSnAjykQtS4/OyG137i5CduwWzZ90nE0sexEJ7cFIcUFbMQLoe+FX++cdYpsL2g+il 9Z98urnB09aiSEVJXXq1ozomV3VvAYZHeIaZ77hzpOm035R4F//MI1JbifkGdLmOCeME AtdsVTXCwL57xnjv01lhS9vkd5cKICH5dBr3pPavL8zEoBbPoiwpKxp+bHtT3OIZoeks 8cMU87d1quRd0WqohvwSXmeL/GDC3eBZKV91KcgYpih6cklib0x6zEPH2vFYxrmqDISb e38A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749777110; x=1750381910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CofZ6mxwdPQ5E5kE6D3I1SRbGpA+t1hpeEYsYL5jGT4=; b=owxIEIWQX/a8d4akFW+Q+FqQg0hHco/kyTUUSxsRtHXSphJpcA4dlTHbVqapjtOk5l 2YANCdNLL/pc3ut8ZulOtrl6wquhjKXHhxV5q0YeKUyFjTmkdFKRkMCTjUFW4zfCkWN4 Tc29+DysNrndL9cMO8MQplKkBOcM5tIUrUBtk/EHzItRGU5jW7kLu4xVpVs3mHxdYhsD ocQnhv2Fz0SrT/DE/nUQrtzSp5N9vBQ7SQoCGQoONe2O5G9PE4l7X6qDNaalGmJZHadF w0V7CVRJsCP0NXfeBpLz4maPzKvtq53vD+Nljxlnv4txlBe1gbhkPKw6BJzBxhNimxDF cWpQ== X-Forwarded-Encrypted: i=1; AJvYcCVaoutjDrNy9NDoFJoepq0TSEdAanb0PI77GFOrJCiyvjbhBs99qY4gyPw5oJMOZ8mjFX+V8gWdNRU=@vger.kernel.org X-Gm-Message-State: AOJu0YwqOjpqigMnarSm6f1LOe5h5F43cJlnwtdwLEa+HWogBAsQXOE7 dON3xLegGrMVHlV841W8cRxj3XmzVUSkAjHYugOROJKuM+36olgpjtXtHQ+YuMh41yc= X-Gm-Gg: ASbGncvaimj717bA8kAPGKFFagorceqrQydhZerp5qzp/ZwltBY3ovHOFlpFg+75qoK UY9M4EUcGKVQl8HXkSAR/y3wd97n3EjYWBlCrht/kdMcgDandR4WxfnXrHmD4BIDhBqjOhW9K06 JHnzYZQ5wNhe353S2zpDVBiDBD1R+OmLf8WriLdOVutTQO3Ny77OHU/TrRSlul4ziEi6gDMnHqq BqkGrV0BimEEFM9bWVbJpPENkqhBsDtW8PrdzCBeeNUQkkVJtxhc2IvQ9a8V5ifxNl8QB4XCUsO ut3x1jh/8xKpoAwpnOzxOGyzTyMheVmgvr0iOOEXv+w0tCdJxA/7EacmooRNOLye+zagpJ9Ug0E Wt+en9YhmRcTT8rRy8ThDzAPc9pvuNFQ= X-Google-Smtp-Source: AGHT+IHhEFwQE/7R/66XtMxO+m/FYMsnTB4goPDIyfodH3kp5NfNiwWnHT2C83VeoHLVhgWdXV8Qgw== X-Received: by 2002:a05:6870:5694:b0:2c2:dfbb:2dbd with SMTP id 586e51a60fabf-2ead4eb6b82mr777124fac.8.1749777110187; Thu, 12 Jun 2025 18:11:50 -0700 (PDT) Received: from presto.localdomain (c-73-228-159-35.hsd1.mn.comcast.net. [73.228.159.35]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-2eac0c17211sm407685fac.18.2025.06.12.18.11.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jun 2025 18:11:49 -0700 (PDT) From: Alex Elder To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dlan@gentoo.org Cc: heylenay@4d2.org, inochiama@outlook.com, guodong@riscstar.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v11 3/6] clk: spacemit: set up reset auxiliary devices Date: Thu, 12 Jun 2025 20:11:35 -0500 Message-ID: <20250613011139.1201702-4-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250613011139.1201702-1-elder@riscstar.com> References: <20250613011139.1201702-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add a new reset_name field to the spacemit_ccu_data structure. If it is non-null, the CCU implements a reset controller, and the name will be used in the name for the auxiliary device that implements it. Define a new type to hold an auxiliary device as well as the regmap pointer that will be needed by CCU reset controllers. Set up code to initialize and add an auxiliary device for any CCU that implements reset functionality. Make it optional for a CCU to implement a clock controller. This doesn't apply to any of the existing CCUs but will for some new ones that will be added soon. Signed-off-by: Alex Elder Reviewed-by: Haylen Chu Reviewed-by: Yixun Lan --- drivers/clk/spacemit/Kconfig | 1 + drivers/clk/spacemit/ccu-k1.c | 104 ++++++++++++++++++++++++++++--- include/soc/spacemit/k1-syscon.h | 12 ++++ 3 files changed, 107 insertions(+), 10 deletions(-) diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig index 4c4df845b3cb2..3854f6ae6d0ea 100644 --- a/drivers/clk/spacemit/Kconfig +++ b/drivers/clk/spacemit/Kconfig @@ -3,6 +3,7 @@ config SPACEMIT_CCU tristate "Clock support for SpacemiT SoCs" depends on ARCH_SPACEMIT || COMPILE_TEST + select AUXILIARY_BUS select MFD_SYSCON help Say Y to enable clock controller unit support for SpacemiT SoCs. diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 801150f4ff0f5..1c9ed434ae93e 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -5,12 +5,15 @@ */ #include +#include #include #include +#include #include #include #include #include +#include #include #include "ccu_common.h" @@ -21,10 +24,13 @@ #include struct spacemit_ccu_data { + const char *reset_name; struct clk_hw **hws; size_t num; }; +static DEFINE_IDA(auxiliary_ids); + /* APBS clocks start, APBS region contains and only contains all PLL clocks */ /* @@ -710,8 +716,9 @@ static struct clk_hw *k1_ccu_pll_hws[] = { }; static const struct spacemit_ccu_data k1_ccu_pll_data = { - .hws = k1_ccu_pll_hws, - .num = ARRAY_SIZE(k1_ccu_pll_hws), + /* The PLL CCU implements no resets */ + .hws = k1_ccu_pll_hws, + .num = ARRAY_SIZE(k1_ccu_pll_hws), }; static struct clk_hw *k1_ccu_mpmu_hws[] = { @@ -751,8 +758,9 @@ static struct clk_hw *k1_ccu_mpmu_hws[] = { }; static const struct spacemit_ccu_data k1_ccu_mpmu_data = { - .hws = k1_ccu_mpmu_hws, - .num = ARRAY_SIZE(k1_ccu_mpmu_hws), + .reset_name = "mpmu-reset", + .hws = k1_ccu_mpmu_hws, + .num = ARRAY_SIZE(k1_ccu_mpmu_hws), }; static struct clk_hw *k1_ccu_apbc_hws[] = { @@ -859,8 +867,9 @@ static struct clk_hw *k1_ccu_apbc_hws[] = { }; static const struct spacemit_ccu_data k1_ccu_apbc_data = { - .hws = k1_ccu_apbc_hws, - .num = ARRAY_SIZE(k1_ccu_apbc_hws), + .reset_name = "apbc-reset", + .hws = k1_ccu_apbc_hws, + .num = ARRAY_SIZE(k1_ccu_apbc_hws), }; static struct clk_hw *k1_ccu_apmu_hws[] = { @@ -929,8 +938,9 @@ static struct clk_hw *k1_ccu_apmu_hws[] = { }; static const struct spacemit_ccu_data k1_ccu_apmu_data = { - .hws = k1_ccu_apmu_hws, - .num = ARRAY_SIZE(k1_ccu_apmu_hws), + .reset_name = "apmu-reset", + .hws = k1_ccu_apmu_hws, + .num = ARRAY_SIZE(k1_ccu_apmu_hws), }; static int spacemit_ccu_register(struct device *dev, @@ -941,6 +951,10 @@ static int spacemit_ccu_register(struct device *dev, struct clk_hw_onecell_data *clk_data; int i, ret; + /* Nothing to do if the CCU does not implement any clocks */ + if (!data->hws) + return 0; + clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num), GFP_KERNEL); if (!clk_data) @@ -981,9 +995,74 @@ static int spacemit_ccu_register(struct device *dev, return ret; } +static void spacemit_cadev_release(struct device *dev) +{ + struct auxiliary_device *adev = to_auxiliary_dev(dev); + + ida_free(&auxiliary_ids, adev->id); + kfree(to_spacemit_ccu_adev(adev)); +} + +static void spacemit_adev_unregister(void *data) +{ + struct auxiliary_device *adev = data; + + auxiliary_device_delete(adev); + auxiliary_device_uninit(adev); +} + +static int spacemit_ccu_reset_register(struct device *dev, + struct regmap *regmap, + const char *reset_name) +{ + struct spacemit_ccu_adev *cadev; + struct auxiliary_device *adev; + int ret; + + /* Nothing to do if the CCU does not implement a reset controller */ + if (!reset_name) + return 0; + + cadev = kzalloc(sizeof(*cadev), GFP_KERNEL); + if (!cadev) + return -ENOMEM; + + cadev->regmap = regmap; + + adev = &cadev->adev; + adev->name = reset_name; + adev->dev.parent = dev; + adev->dev.release = spacemit_cadev_release; + adev->dev.of_node = dev->of_node; + ret = ida_alloc(&auxiliary_ids, GFP_KERNEL); + if (ret < 0) + goto err_free_cadev; + adev->id = ret; + + ret = auxiliary_device_init(adev); + if (ret) + goto err_free_aux_id; + + ret = auxiliary_device_add(adev); + if (ret) { + auxiliary_device_uninit(adev); + return ret; + } + + return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev); + +err_free_aux_id: + ida_free(&auxiliary_ids, adev->id); +err_free_cadev: + kfree(cadev); + + return ret; +} + static int k1_ccu_probe(struct platform_device *pdev) { struct regmap *base_regmap, *lock_regmap = NULL; + const struct spacemit_ccu_data *data; struct device *dev = &pdev->dev; int ret; @@ -1012,11 +1091,16 @@ static int k1_ccu_probe(struct platform_device *pdev) "failed to get lock regmap\n"); } - ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, - of_device_get_match_data(dev)); + data = of_device_get_match_data(dev); + + ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data); if (ret) return dev_err_probe(dev, ret, "failed to register clocks\n"); + ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name); + if (ret) + return dev_err_probe(dev, ret, "failed to register resets\n"); + return 0; } diff --git a/include/soc/spacemit/k1-syscon.h b/include/soc/spacemit/k1-syscon.h index 039a448c51a07..53eff7691f33d 100644 --- a/include/soc/spacemit/k1-syscon.h +++ b/include/soc/spacemit/k1-syscon.h @@ -5,6 +5,18 @@ #ifndef __SOC_K1_SYSCON_H__ #define __SOC_K1_SYSCON_H__ +/* Auxiliary device used to represent a CCU reset controller */ +struct spacemit_ccu_adev { + struct auxiliary_device adev; + struct regmap *regmap; +}; + +static inline struct spacemit_ccu_adev * +to_spacemit_ccu_adev(struct auxiliary_device *adev) +{ + return container_of(adev, struct spacemit_ccu_adev, adev); +} + /* APBS register offset */ #define APBS_PLL1_SWCR1 0x100 #define APBS_PLL1_SWCR2 0x104 -- 2.45.2