* [PATCH 0/3] SM8750 GPU clocks
@ 2025-07-08 12:47 Konrad Dybcio
2025-07-08 12:47 ` [PATCH 1/3] dt-bindings: clock: qcom: Add " Konrad Dybcio
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Konrad Dybcio @ 2025-07-08 12:47 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio
Cc: Marijn Suijten, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Konrad Dybcio
This series brings a driver for GPU clock controllers (there are two
now, but that's almost a cosmetic change) on 8750 and wires up the GPU
SMMU instance.
No external dependencies to the best of my knowledge.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
Konrad Dybcio (3):
dt-bindings: clock: qcom: Add SM8750 GPU clocks
clk: qcom: Add a driver for SM8750 GPU clocks
arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes
.../bindings/clock/qcom,sm8450-gpucc.yaml | 5 +
.../bindings/clock/qcom,sm8750-gxcc.yaml | 58 +++
arch/arm64/boot/dts/qcom/sm8750.dtsi | 63 +++
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gpucc-sm8750.c | 524 +++++++++++++++++++++
include/dt-bindings/clock/qcom,sm8750-gpucc.h | 53 +++
7 files changed, 713 insertions(+)
---
base-commit: 58ba80c4740212c29a1cf9b48f588e60a7612209
change-id: 20250708-topic-8750_gpucc-2e68defb27d3
Best regards,
--
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 1/3] dt-bindings: clock: qcom: Add SM8750 GPU clocks 2025-07-08 12:47 [PATCH 0/3] SM8750 GPU clocks Konrad Dybcio @ 2025-07-08 12:47 ` Konrad Dybcio 2025-07-10 21:43 ` Rob Herring 2025-07-08 12:47 ` [PATCH 2/3] clk: qcom: Add a driver for " Konrad Dybcio 2025-07-08 12:47 ` [PATCH 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes Konrad Dybcio 2 siblings, 1 reply; 5+ messages in thread From: Konrad Dybcio @ 2025-07-08 12:47 UTC (permalink / raw) To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio Cc: Marijn Suijten, linux-arm-msm, linux-clk, devicetree, linux-kernel, Konrad Dybcio From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> The SM8750 features a "traditional" GPU_CC block, much of which is controlled through the GMU microcontroller. Additionally, there's an separate GX_CC block, where the GX GDSC is moved. Add bindings to accommodate for that. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> --- .../bindings/clock/qcom,sm8450-gpucc.yaml | 5 ++ .../bindings/clock/qcom,sm8750-gxcc.yaml | 58 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,sm8750-gpucc.h | 53 ++++++++++++++++++++ 3 files changed, 116 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index 02968632fb3af34d6b3983a6a24aa742db1d59b1..d1b3557ab344b071d16dba4d5c6a267b7ab70573 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -20,6 +20,7 @@ description: | include/dt-bindings/clock/qcom,sm8550-gpucc.h include/dt-bindings/reset/qcom,sm8450-gpucc.h include/dt-bindings/reset/qcom,sm8650-gpucc.h + include/dt-bindings/reset/qcom,sm8750-gpucc.h include/dt-bindings/reset/qcom,x1e80100-gpucc.h properties: @@ -31,6 +32,7 @@ properties: - qcom,sm8475-gpucc - qcom,sm8550-gpucc - qcom,sm8650-gpucc + - qcom,sm8750-gpucc - qcom,x1e80100-gpucc - qcom,x1p42100-gpucc @@ -40,6 +42,9 @@ properties: - description: GPLL0 main branch source - description: GPLL0 div branch source + power-domains: + maxItems: 1 + required: - compatible - clocks diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8750-gxcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8750-gxcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..f35839193d18b608e177b4d6561827dfa98c9aa1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8750-gxcc.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8750-gxcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM8750 + +maintainers: + - Konrad Dybcio <konradybcio@kernel.org> + +description: | + Qualcomm graphics clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/reset/qcom,sm8750-gpucc.h + +properties: + compatible: + enum: + - qcom,sm8750-gxcc + + reg: + maxItems: 1 + + power-domains: + maxItems: 3 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - power-domains + - '#power-domain-cells' + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8750-gpucc.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d64000 { + compatible = "qcom,sm8750-gxcc"; + reg = <0x0 0x03d64000 0x0 0x6000>; + power-domains = <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_MXC>, + <&gpucc GPU_CC_CX_GDSC>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm8750-gpucc.h b/include/dt-bindings/clock/qcom,sm8750-gpucc.h new file mode 100644 index 0000000000000000000000000000000000000000..98e2f5df78740bf298c6b1065972d7e58ee81713 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8750-gpucc.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CX_ACCU_SHIFT_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_DEMET_CLK 7 +#define GPU_CC_DPM_CLK 8 +#define GPU_CC_FF_CLK_SRC 9 +#define GPU_CC_FREQ_MEASURE_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_ACCU_SHIFT_CLK 12 +#define GPU_CC_GX_ACD_AHB_FF_CLK 13 +#define GPU_CC_GX_AHB_FF_CLK 14 +#define GPU_CC_GX_GMU_CLK 15 +#define GPU_CC_GX_RCG_AHB_FF_CLK 16 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_DIV_CLK_SRC 21 +#define GPU_CC_MEMNOC_GFX_CLK 22 +#define GPU_CC_PLL0 23 +#define GPU_CC_PLL0_OUT_EVEN 24 +#define GPU_CC_RSCC_HUB_AON_CLK 25 +#define GPU_CC_RSCC_XO_AON_CLK 26 +#define GPU_CC_SLEEP_CLK 27 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 + +/* GPU_CC resets */ +#define GPU_CC_GPU_CC_CB_BCR 0 +#define GPU_CC_GPU_CC_CX_BCR 1 +#define GPU_CC_GPU_CC_FAST_HUB_BCR 2 +#define GPU_CC_GPU_CC_FF_BCR 3 +#define GPU_CC_GPU_CC_GMU_BCR 4 +#define GPU_CC_GPU_CC_GX_BCR 5 +#define GPU_CC_GPU_CC_XO_BCR 6 + +/* GX_CC power domains */ +#define GX_CC_GX_GDSC 0 + +#endif -- 2.50.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/3] dt-bindings: clock: qcom: Add SM8750 GPU clocks 2025-07-08 12:47 ` [PATCH 1/3] dt-bindings: clock: qcom: Add " Konrad Dybcio @ 2025-07-10 21:43 ` Rob Herring 0 siblings, 0 replies; 5+ messages in thread From: Rob Herring @ 2025-07-10 21:43 UTC (permalink / raw) To: Konrad Dybcio Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Krzysztof Kozlowski, Conor Dooley, Marijn Suijten, linux-arm-msm, linux-clk, devicetree, linux-kernel, Konrad Dybcio On Tue, Jul 08, 2025 at 02:47:20PM +0200, Konrad Dybcio wrote: > From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > > The SM8750 features a "traditional" GPU_CC block, much of which is > controlled through the GMU microcontroller. Additionally, there's > an separate GX_CC block, where the GX GDSC is moved. > > Add bindings to accommodate for that. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > --- > .../bindings/clock/qcom,sm8450-gpucc.yaml | 5 ++ > .../bindings/clock/qcom,sm8750-gxcc.yaml | 58 ++++++++++++++++++++++ > include/dt-bindings/clock/qcom,sm8750-gpucc.h | 53 ++++++++++++++++++++ > 3 files changed, 116 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml > index 02968632fb3af34d6b3983a6a24aa742db1d59b1..d1b3557ab344b071d16dba4d5c6a267b7ab70573 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml > @@ -20,6 +20,7 @@ description: | > include/dt-bindings/clock/qcom,sm8550-gpucc.h > include/dt-bindings/reset/qcom,sm8450-gpucc.h > include/dt-bindings/reset/qcom,sm8650-gpucc.h > + include/dt-bindings/reset/qcom,sm8750-gpucc.h > include/dt-bindings/reset/qcom,x1e80100-gpucc.h > > properties: > @@ -31,6 +32,7 @@ properties: > - qcom,sm8475-gpucc > - qcom,sm8550-gpucc > - qcom,sm8650-gpucc > + - qcom,sm8750-gpucc > - qcom,x1e80100-gpucc > - qcom,x1p42100-gpucc > > @@ -40,6 +42,9 @@ properties: > - description: GPLL0 main branch source > - description: GPLL0 div branch source > > + power-domains: > + maxItems: 1 > + > required: > - compatible > - clocks > diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8750-gxcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8750-gxcc.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..f35839193d18b608e177b4d6561827dfa98c9aa1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,sm8750-gxcc.yaml > @@ -0,0 +1,58 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,sm8750-gxcc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Graphics Clock & Reset Controller on SM8750 > + > +maintainers: > + - Konrad Dybcio <konradybcio@kernel.org> > + > +description: | > + Qualcomm graphics clock control module provides the clocks, resets and power > + domains on Qualcomm SoCs. > + > + See also:: Don't need double colon. > + include/dt-bindings/reset/qcom,sm8750-gpucc.h > + > +properties: > + compatible: > + enum: > + - qcom,sm8750-gxcc > + > + reg: > + maxItems: 1 > + > + power-domains: > + maxItems: 3 You need to define what each power domain is. > + > + '#power-domain-cells': > + const: 1 > + > +required: > + - compatible > + - power-domains > + - '#power-domain-cells' > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,sm8750-gpucc.h> > + #include <dt-bindings/power/qcom,rpmhpd.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + clock-controller@3d64000 { > + compatible = "qcom,sm8750-gxcc"; > + reg = <0x0 0x03d64000 0x0 0x6000>; > + power-domains = <&rpmhpd RPMHPD_GFX>, > + <&rpmhpd RPMHPD_MXC>, > + <&gpucc GPU_CC_CX_GDSC>; > + #power-domain-cells = <1>; > + }; > + }; > +... > diff --git a/include/dt-bindings/clock/qcom,sm8750-gpucc.h b/include/dt-bindings/clock/qcom,sm8750-gpucc.h > new file mode 100644 > index 0000000000000000000000000000000000000000..98e2f5df78740bf298c6b1065972d7e58ee81713 > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,sm8750-gpucc.h > @@ -0,0 +1,53 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H > +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H > + > +/* GPU_CC clocks */ > +#define GPU_CC_AHB_CLK 0 > +#define GPU_CC_CB_CLK 1 > +#define GPU_CC_CX_ACCU_SHIFT_CLK 2 > +#define GPU_CC_CX_FF_CLK 3 > +#define GPU_CC_CX_GMU_CLK 4 > +#define GPU_CC_CXO_AON_CLK 5 > +#define GPU_CC_CXO_CLK 6 > +#define GPU_CC_DEMET_CLK 7 > +#define GPU_CC_DPM_CLK 8 > +#define GPU_CC_FF_CLK_SRC 9 > +#define GPU_CC_FREQ_MEASURE_CLK 10 > +#define GPU_CC_GMU_CLK_SRC 11 > +#define GPU_CC_GX_ACCU_SHIFT_CLK 12 > +#define GPU_CC_GX_ACD_AHB_FF_CLK 13 > +#define GPU_CC_GX_AHB_FF_CLK 14 > +#define GPU_CC_GX_GMU_CLK 15 > +#define GPU_CC_GX_RCG_AHB_FF_CLK 16 > +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 17 > +#define GPU_CC_HUB_AON_CLK 18 > +#define GPU_CC_HUB_CLK_SRC 19 > +#define GPU_CC_HUB_CX_INT_CLK 20 > +#define GPU_CC_HUB_DIV_CLK_SRC 21 > +#define GPU_CC_MEMNOC_GFX_CLK 22 > +#define GPU_CC_PLL0 23 > +#define GPU_CC_PLL0_OUT_EVEN 24 > +#define GPU_CC_RSCC_HUB_AON_CLK 25 > +#define GPU_CC_RSCC_XO_AON_CLK 26 > +#define GPU_CC_SLEEP_CLK 27 > + > +/* GPU_CC power domains */ > +#define GPU_CC_CX_GDSC 0 > + > +/* GPU_CC resets */ > +#define GPU_CC_GPU_CC_CB_BCR 0 > +#define GPU_CC_GPU_CC_CX_BCR 1 > +#define GPU_CC_GPU_CC_FAST_HUB_BCR 2 > +#define GPU_CC_GPU_CC_FF_BCR 3 > +#define GPU_CC_GPU_CC_GMU_BCR 4 > +#define GPU_CC_GPU_CC_GX_BCR 5 > +#define GPU_CC_GPU_CC_XO_BCR 6 > + > +/* GX_CC power domains */ > +#define GX_CC_GX_GDSC 0 > + > +#endif > > -- > 2.50.0 > ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/3] clk: qcom: Add a driver for SM8750 GPU clocks 2025-07-08 12:47 [PATCH 0/3] SM8750 GPU clocks Konrad Dybcio 2025-07-08 12:47 ` [PATCH 1/3] dt-bindings: clock: qcom: Add " Konrad Dybcio @ 2025-07-08 12:47 ` Konrad Dybcio 2025-07-08 12:47 ` [PATCH 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes Konrad Dybcio 2 siblings, 0 replies; 5+ messages in thread From: Konrad Dybcio @ 2025-07-08 12:47 UTC (permalink / raw) To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio Cc: Marijn Suijten, linux-arm-msm, linux-clk, devicetree, linux-kernel, Konrad Dybcio From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> The SM8750's GFX hardware is largely clocked by two domains: GPU_CC (which is very similar to the ones on previous SoCs) and GX_CC (where the GX GDSC now resides). As usual, the GMU drives most of the clocks and Linux only manages a subset required to boot it (and the SMMU) up. Add a driver to accommodate for that. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm8750.c | 524 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 534 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 36d6e6e1e7f0162d53f02f39125f4593517e0dba..9f430fcee3ef4e44dbf8f6277d7bf85888dedd59 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1295,6 +1295,15 @@ config SM_GPUCC_8650 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. +config SM_GPUCC_8750 + tristate "SM8750 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST + select SM_GCC_8750 + help + Support for the graphics clock controller on SM8750 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_LPASSCC_6115 tristate "SM6115 Low Power Audio Subsystem (LPASS) Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index ab59434338bb6d6f49b0af94ff0f85cb386a16db..b55f373d71e136eaa279ed3ea8e8714119ecfd70 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -161,6 +161,7 @@ obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o obj-$(CONFIG_SM_GPUCC_8650) += gpucc-sm8650.o +obj-$(CONFIG_SM_GPUCC_8750) += gpucc-sm8750.o obj-$(CONFIG_SM_LPASSCC_6115) += lpasscc-sm6115.o obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o obj-$(CONFIG_SM_TCSRCC_8650) += tcsrcc-sm8650.o diff --git a/drivers/clk/qcom/gpucc-sm8750.c b/drivers/clk/qcom/gpucc-sm8750.c new file mode 100644 index 0000000000000000000000000000000000000000..ea8e5a87778d87745f29b115185ba7b0fa4c43e1 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm8750.c @@ -0,0 +1,524 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,sm8750-gpucc.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_EVEN, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL0_OUT_ODD, +}; + +static const struct pll_vco taycan_elu_vco[] = { + { 249600000, 2500000000, 0 }, +}; + +static const struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x34, + .alpha = 0x1555, + .config_ctl_val = 0x19660387, + .config_ctl_hi_val = 0x098060a0, + .config_ctl_hi1_val = 0xb416cb20, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000002, +}; + +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .config = &gpu_cc_pll0_config, + .vco_table = taycan_elu_vco, + .num_vco = ARRAY_SIZE(taycan_elu_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_taycan_elu_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpu_cc_pll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even = { + .offset = 0x0, + .post_div_shift = 10, + .post_div_table = post_div_table_gpu_cc_pll0_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_pll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, + }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL0_OUT_EVEN, 2 }, + { P_GPU_CC_PLL0_OUT_ODD, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll0_out_even.clkr.hw }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .fw_name = "gpll0_out_main" }, + { .fw_name = "gpll0_out_main_div" }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(500000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(687500000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x9318, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src = { + .cmd_rcgr = 0x93ec, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_hub_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_div_clk_src = { + .reg = 0x942c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x90bc, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x90bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_accu_shift_clk = { + .halt_reg = 0x910c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x910c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cx_accu_shift_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x90d4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x90d4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cx_gmu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x90e4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x90e4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_demet_clk = { + .halt_reg = 0x9010, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_demet_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_dpm_clk = { + .halt_reg = 0x9110, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9110, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_dpm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_freq_measure_clk = { + .halt_reg = 0x900c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x900c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_freq_measure_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_accu_shift_clk = { + .halt_reg = 0x9070, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9070, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gx_accu_shift_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gmu_clk = { + .halt_reg = 0x9060, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9060, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gx_gmu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x7000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk = { + .halt_reg = 0x93e8, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x93e8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_aon_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk = { + .halt_reg = 0x90e8, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x90e8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_cx_int_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk = { + .halt_reg = 0x90f4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x90f4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_memnoc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cc_cx_gdsc = { + .gdscr = 0x9080, + .gds_hw_ctrl = 0x9094, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x8, + .pd = { + .name = "gpu_cc_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct clk_regmap *gpu_cc_sm8750_clocks[] = { + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr, + [GPU_CC_DPM_CLK] = &gpu_cc_dpm_clk.clkr, + [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr, + [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_DIV_CLK_SRC] = &gpu_cc_hub_div_clk_src.clkr, + [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_PLL0_OUT_EVEN] = &gpu_cc_pll0_out_even.clkr, +}; + +static struct gdsc *gpu_cc_sm8750_gdscs[] = { + [GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_sm8750_resets[] = { + [GPU_CC_GPU_CC_XO_BCR] = { 0x9000 }, + [GPU_CC_GPU_CC_GX_BCR] = { 0x905c }, + [GPU_CC_GPU_CC_CX_BCR] = { 0x907c }, + [GPU_CC_GPU_CC_GMU_BCR] = { 0x9314 }, + [GPU_CC_GPU_CC_CB_BCR] = { 0x93a0 }, + [GPU_CC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 }, +}; + +static const struct regmap_config gpu_cc_sm8750_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9800, + .fast_io = true, +}; + +static struct clk_alpha_pll *gpu_cc_alpha_plls[] = { + &gpu_cc_pll0, +}; + +static u32 gpu_cc_sm8750_critical_cbcrs[] = { + 0x9004, /* GPU_CC_RSCC_XO_AON_CLK */ + 0x9008, /* GPU_CC_CXO_AON_CLK */ + 0x9064, /* GPU_CC_GX_AHB_FF_CLK */ + 0x90cc, /* GPU_CC_SLEEP_CLK */ + 0x93a4, /* GPU_CC_CB_CLK */ + 0x93a8, /* GPU_CC_RSCC_HUB_AON_CLK */ +}; + +static struct qcom_cc_driver_data gpu_cc_sm8750_driver_data = { + .alpha_plls = gpu_cc_alpha_plls, + .num_alpha_plls = ARRAY_SIZE(gpu_cc_alpha_plls), + .clk_cbcrs = gpu_cc_sm8750_critical_cbcrs, + .num_clk_cbcrs = ARRAY_SIZE(gpu_cc_sm8750_critical_cbcrs), +}; + +static const struct qcom_cc_desc gpu_cc_sm8750_desc = { + .config = &gpu_cc_sm8750_regmap_config, + .clks = gpu_cc_sm8750_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sm8750_clocks), + .resets = gpu_cc_sm8750_resets, + .num_resets = ARRAY_SIZE(gpu_cc_sm8750_resets), + .gdscs = gpu_cc_sm8750_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_sm8750_gdscs), + .driver_data = &gpu_cc_sm8750_driver_data, +}; + +static const struct of_device_id gpu_cc_sm8750_match_table[] = { + { .compatible = "qcom,sm8750-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm8750_match_table); + +static int gpu_cc_sm8750_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gpu_cc_sm8750_desc); +} + +static struct platform_driver gpu_cc_sm8750_driver = { + .probe = gpu_cc_sm8750_probe, + .driver = { + .name = "sm8750-gpucc", + .of_match_table = gpu_cc_sm8750_match_table, + }, +}; +module_platform_driver(gpu_cc_sm8750_driver); + +static struct gdsc gx_cc_gx_gdsc = { + .gdscr = 0x4024, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gx_cc_gx_gdsc", + .power_on = gdsc_gx_do_nothing_enable, + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc *gx_cc_gdscs[] = { + [GX_CC_GX_GDSC] = &gx_cc_gx_gdsc, +}; + +static const struct regmap_config gx_cc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x6000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gx_cc_sm8750_desc = { + .config = &gx_cc_regmap_config, + .gdscs = gx_cc_gdscs, + .num_gdscs = ARRAY_SIZE(gx_cc_gdscs), + .use_rpm = true, +}; + +static const struct of_device_id gx_cc_sm8750_match_table[] = { + { .compatible = "qcom,sm8750-gxcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gx_cc_sm8750_match_table); + +static int gx_cc_sm8750_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gx_cc_sm8750_desc); +} + +static struct platform_driver gx_cc_sm8750_driver = { + .probe = gx_cc_sm8750_probe, + .driver = { + .name = "gx_cc-sm8750", + .of_match_table = gx_cc_sm8750_match_table, + }, +}; +module_platform_driver(gx_cc_sm8750_driver); + +MODULE_DESCRIPTION("QTI GPU_CC SM8750 Driver"); +MODULE_LICENSE("GPL"); -- 2.50.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes 2025-07-08 12:47 [PATCH 0/3] SM8750 GPU clocks Konrad Dybcio 2025-07-08 12:47 ` [PATCH 1/3] dt-bindings: clock: qcom: Add " Konrad Dybcio 2025-07-08 12:47 ` [PATCH 2/3] clk: qcom: Add a driver for " Konrad Dybcio @ 2025-07-08 12:47 ` Konrad Dybcio 2 siblings, 0 replies; 5+ messages in thread From: Konrad Dybcio @ 2025-07-08 12:47 UTC (permalink / raw) To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio Cc: Marijn Suijten, linux-arm-msm, linux-clk, devicetree, linux-kernel, Konrad Dybcio From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this is simply a separate block housing the GX GDSC) nodes, required to power up the graphics-related hardware. Make use of it by enabling the associated IOMMU as well. The GPU itself needs some more work and will be enabled later. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 63 ++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 4643705021c6ca095a16d8d7cc3adac920b21e82..ca0770a34bed64183185aedde04f1bb96eebfa91 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,sm8750-gcc.h> +#include <dt-bindings/clock/qcom,sm8750-gpucc.h> #include <dt-bindings/clock/qcom,sm8750-tcsr.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> @@ -3154,6 +3155,68 @@ tcsrcc: clock-controller@f204008 { #reset-cells = <1>; }; + gxcc: clock-controller@3d64000 { + compatible = "qcom,sm8750-gxcc"; + reg = <0x0 0x03d64000 0x0 0x6000>; + power-domains = <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_MXC>, + <&gpucc GPU_CC_CX_GDSC>; + #power-domain-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm8750-gpucc"; + reg = <0x0 0x03d90000 0x0 0x9800>; + + clocks = <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8750-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "hlos"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x15000000 0x0 0x100000>; -- 2.50.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-07-10 21:43 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-07-08 12:47 [PATCH 0/3] SM8750 GPU clocks Konrad Dybcio 2025-07-08 12:47 ` [PATCH 1/3] dt-bindings: clock: qcom: Add " Konrad Dybcio 2025-07-10 21:43 ` Rob Herring 2025-07-08 12:47 ` [PATCH 2/3] clk: qcom: Add a driver for " Konrad Dybcio 2025-07-08 12:47 ` [PATCH 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes Konrad Dybcio
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