From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7489F2E92AD; Fri, 11 Jul 2025 14:52:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752245559; cv=none; b=tEFiVi23bCdPElF/kp618EMfCKkvUTyrpHEvUf3R3TWra+rWFuQSGRyPcOdlCnzcG4bx1qaOHX7n6pDnWmI533t29nI2tX4UJlrqEchbpntKIc9jWxuJ7idSzD/YUhqL+3IMHdYzZz0vHT2NSYAQjm6vnr11zfpgudnMcLauQ4Y= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752245559; c=relaxed/simple; bh=ZLo3mNVzNbVvAP4/5XoYEPKh9ndtjxqdnpGe9hsHCnY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=nvWmML+1wLjkqQmShdAJfcvmJL/49tGt5Yb0gTAbcTPiCHE5HzEf8cy6ZO1jJevwGr8bIhhAuwFV8ADI7mTVVuosVkoW4TM/wB6rBDEcmFWWioLhJnO6AIUhvTK+xRPkRk2U/np1HZiVNaAbLUhQSo+C4mrGDJA2NxB6l9uw2Q0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=1IsJsXu9; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="1IsJsXu9" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56BChEqB006517; Fri, 11 Jul 2025 16:52:22 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= Bc/v1axb6utVOQjnTP/Qv3nkmKL0VE0rqaXdGeFNbUU=; b=1IsJsXu9DcR4m3aR SNzkoYkvHSyhhJHIvJeZ0VLT8Twer2llLePGtWpuzXvGtXPCCcFPkqJ2vIbvFDbR 1AOp6UMm+RoVIDrBk7MYYlavG1EWdGL8NA7P28m/tvEg0zmn+27/S3weo7SmVoZi /8J+H3c8IyyL8AzSk+w4QnYml9JCyxyqpAt+eBUP7CMKF3t5pe2JiFK4HxMEjywW 3uVrsWNsNWX03P/xJIYGNU8RD1JCLHAW1XOou0PKpg8mfM/XkOs6onxeoJSNZnyY MXml9+4RKOw878wD82leu0DUio3DPKPju3KL9fEWndmebboqEEMpQnlX3WmyixGV aJn9fw== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 47psfmyt7v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 11 Jul 2025 16:52:22 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 71BD440049; Fri, 11 Jul 2025 16:51:02 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 913D4B52715; Fri, 11 Jul 2025 16:49:19 +0200 (CEST) Received: from localhost (10.252.16.187) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 11 Jul 2025 16:49:19 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Fri, 11 Jul 2025 16:49:00 +0200 Subject: [PATCH v2 08/16] dt-bindings: perf: stm32: introduce DDRPERFM dt-bindings Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-ID: <20250711-ddrperfm-upstream-v2-8-cdece720348f@foss.st.com> References: <20250711-ddrperfm-upstream-v2-0-cdece720348f@foss.st.com> In-Reply-To: <20250711-ddrperfm-upstream-v2-0-cdece720348f@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-7616d X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-11_03,2025-07-09_01,2025-03-28_01 DDRPERFM is the DDR Performance Monitor embedded in STM32MPU SoC. It allows to monitor DDR events that come from the DDR Controller such as read or write events. Signed-off-by: Clément Le Goffic --- .../devicetree/bindings/perf/st,stm32-ddr-pmu.yaml | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml b/Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml new file mode 100644 index 000000000000..3c123a4a0e80 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/st,stm32-ddr-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Clément Le Goffic + +title: STMicroelectronics STM32 DDR Performance Monitor (DDRPERFM) + +properties: + compatible: + enum: + - st,stm32mp131-ddr-pmu + - st,stm32mp151-ddr-pmu + - st,stm32mp251-ddr-pmu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + access-controllers: + minItems: 1 + maxItems: 2 + + memory-channel: + description: + The memory channel this DDRPERFM is attached to. + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: st,stm32mp131-ddr-pmu + then: + required: + - clocks + - resets + + - if: + properties: + compatible: + contains: + const: st,stm32mp251-ddr-pmu + then: + required: + - access-controllers + - memory-channel + +additionalProperties: false + +examples: + - | + #include + #include + + perf@5a007000 { + compatible = "st,stm32mp151-ddr-pmu"; + reg = <0x5a007000 0x400>; + clocks = <&rcc DDRPERFM>; + resets = <&rcc DDRPERFM_R>; + }; + + - | + ddr_channel: ddr3-channel { + compatible = "jedec,ddr3-channel"; + io-width = <16>; + }; + + perf@48041000 { + compatible = "st,stm32mp251-ddr-pmu"; + reg = <0x48041000 0x400>; + access-controllers = <&rcc 104>; + memory-channel = <&ddr_channel>; + }; -- 2.43.0