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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.16.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:16:41 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 00/19] tegra-video: add CSI support for Tegra20 and Tegra30 Date: Tue, 19 Aug 2025 15:16:12 +0300 Message-ID: <20250819121631.84280-1-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for MIPI CSI device found in Tegra20 and Tegra30 SoC along with a set of changes required for that. Svyatoslav Ryhel (19): clk: tegra: init CSUS clock for Tegra20 and Tegra30 dt-bindings: clock: tegra20: Add IDs for CSI PAD clocks clk: tegra30: add CSI PAD clock gates dt-bindings: display: tegra: document Tegra30 VIP staging: media: tegra-video: expand VI and VIP support to Tegra30 staging: media: tegra-video: csi: move CSI helpers to header staging: media: tegra-video: csi: parametrize MIPI calibration device presence staging: media: tegra-video: vi: adjust get_selection op check staging: media: tegra-video: vi: add flip controls only if no source controls are provided staging: media: tegra-video: tegra20: set correct maximum width and height staging: media: tegra-video: tegra20: add support for second output of VI staging: media: tegra-video: tegra20: simplify format align calculations staging: media: tegra-video: tegra20: set VI HW revision staging: media: tegra-video: tegra20: increase maximum VI clock frequency staging: media: tegra-video: tegra20: expand format support with RAW8/10 and YUV422 1X16 staging: media: tegra-video: tegra20: adjust luma buffer stride dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI ARM: tegra: add CSI binding for Tegra20 and Tegra30 staging: media: tegra-video: add CSI support for Tegra20 and Tegra30 .../display/tegra/nvidia,tegra20-vip.yaml | 1 + .../display/tegra/nvidia,tegra210-csi.yaml | 78 +- arch/arm/boot/dts/nvidia/tegra20.dtsi | 17 +- arch/arm/boot/dts/nvidia/tegra30.dtsi | 19 +- drivers/clk/tegra/clk-tegra20.c | 1 + drivers/clk/tegra/clk-tegra30.c | 16 +- drivers/staging/media/tegra-video/Makefile | 1 + drivers/staging/media/tegra-video/csi.c | 35 +- drivers/staging/media/tegra-video/csi.h | 11 + drivers/staging/media/tegra-video/tegra20.c | 771 +++++++++++++++--- drivers/staging/media/tegra-video/tegra210.c | 1 + drivers/staging/media/tegra-video/vi.c | 20 +- drivers/staging/media/tegra-video/vi.h | 4 +- drivers/staging/media/tegra-video/video.c | 6 + drivers/staging/media/tegra-video/vip.c | 5 +- include/dt-bindings/clock/tegra30-car.h | 4 +- 16 files changed, 842 insertions(+), 148 deletions(-) -- 2.48.1