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[190.12.77.24]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-324e257809esm2606455a91.24.2025.08.20.07.59.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Aug 2025 07:59:12 -0700 (PDT) From: Denzeel Oliva Subject: [PATCH v2 0/3] clk: samsung: exynos990: CMU_TOP fixes (mux regs, widths, factors) Date: Wed, 20 Aug 2025 09:57:21 -0500 Message-Id: <20250820-2-v2-0-bd45e196d4c4@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAFLipWgC/02Myw6DIBBFf8XMujRAtGBX/Y/GBY9RJ6nSQEM0h n8vddXlubnnHJAwEia4NwdEzJQorBXkpQE3m3VCRr4ySC47rkXPJDP25rT1I1deQf29I460nY3 nUHmm9AlxP5NZ/NZ/OwvGGerWtsrqrnf4mBZDr6sLCwyllC83XA3XkgAAAA== X-Change-ID: 20250819-2-ab6c8bdf07d7 To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Denzeel Oliva X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755701948; l=1078; i=wachiturroxd150@gmail.com; s=20250819; h=from:subject:message-id; bh=W68k0m74FKq6rT8PIZd3IxIAE0Dive0UITAv+zCe5+g=; b=u9TvdLut9T/l2pJ/hsZbjYfVLj1dhqtUVvMITE8G9SK/eUYZGzp7h0OtJjP51LUJjTi8syUTb /JlJJyTwBsfCogQd8FAkonDyS60JQ0a7+mCVss5qZP2pgSvtW4nVz5E X-Developer-Key: i=wachiturroxd150@gmail.com; a=ed25519; pk=qNvcL0Ehm3chrW9jFA2JaPVgubN5mHH//uriMxR/DlI= Hi, Two small fixes for Exynos990 CMU_TOP: Correct PLL mux register selection (use PLL_CON0), add DPU_BUS and CMUREF mux/div, and update clock IDs. Fix mux/div bit widths and replace a few bogus divs with fixed-factor clocks (HSI1/2 PCIe, USBDP debug); also fix OTP rate. Changes in v2: - In the first commit the divratio of PLL_SHARED0_DIV3 should not be changed. Please review. Denzeel Oliva --- Denzeel Oliva (3): clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors dt-bindings: clock: exynos990: Reorder IDs clocks and extend clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF drivers/clk/samsung/clk-exynos990.c | 154 +++++++++++++++---------- include/dt-bindings/clock/samsung,exynos990.h | 402 ++++++++++++++++++++++++++++++++-------------------------------- 2 files changed, 297 insertions(+), 259 deletions(-) --- base-commit: 886e5e7b0432360842303d587bb4a65d10741ae8 change-id: 20250819-2-ab6c8bdf07d7 Best regards, -- Denzeel Oliva