* [PATCH 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support
@ 2025-08-20 17:17 Biju
2025-08-20 17:17 ` [PATCH 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks Biju
2025-08-20 17:17 ` [PATCH 02/11] clk: renesas: r9a09g047: Add USB3.0 clocks/resets Biju
0 siblings, 2 replies; 6+ messages in thread
From: Biju @ 2025-08-20 17:17 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Vinod Koul,
Kishon Vijay Abraham I, Philipp Zabel, Mathias Nyman,
Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-clk, linux-phy, linux-usb, devicetree,
Wesley Cheng, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add RZ/G3E USB3.2 Gen1 Host Controller and PHY support. The USB3HOST
is compliant with the Universal Serial Bus 3.2 Specification Revision 1.0.
- Supports 1 downstream USB receptacles
- Number of SSP Gen2 or SS ports: 1
- Number of HS or FS or LS ports: 1
- Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps),
High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps).
- Supports all transfer-types: Control, Bulk, Interrupt, Isochronous, and
these split-transactions.
- Supports Power Control and Over Current Detection.
Biju Das (11):
dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks
clk: renesas: r9a09g047: Add USB3.0 clocks/resets
dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY
phy: renesas: Add Renesas RZ/G3E USB3.0 PHY driver
usb: host: xhci-rcar: Move R-Car reg definitions
dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
usb: host: xhci-plat: Add .post_resume_quirk for struct xhci_plat_priv
usb: host: xhci-rcar: Add Renesas RZ/G3E USB3 Host driver support
arm64: dts: renesas: r9a09g047: Add USB3 PHY/Host nodes
arm64: dts: renesas: r9a09g047e57-smarc: Enable USB3HOST
arm64: defconfig: Enable RZ/G3E USB3 PHY driver
.../bindings/phy/renesas,rzg3e-usb3-phy.yaml | 63 +++++
.../bindings/usb/renesas,rzg3e-xhci.yaml | 84 ++++++
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 30 +++
.../boot/dts/renesas/r9a09g047e57-smarc.dts | 10 +
.../boot/dts/renesas/renesas-smarc2.dtsi | 8 +
arch/arm64/configs/defconfig | 1 +
drivers/clk/renesas/r9a09g047-cpg.c | 9 +-
drivers/phy/renesas/Kconfig | 7 +
drivers/phy/renesas/Makefile | 1 +
drivers/phy/renesas/phy-rzg3e-usb3.c | 249 ++++++++++++++++++
drivers/usb/host/Kconfig | 2 +-
drivers/usb/host/xhci-plat.c | 14 +
drivers/usb/host/xhci-plat.h | 1 +
drivers/usb/host/xhci-rcar-regs.h | 49 ++++
drivers/usb/host/xhci-rcar.c | 100 +++----
drivers/usb/host/xhci-rzg3e-regs.h | 12 +
.../dt-bindings/clock/renesas,r9a09g047-cpg.h | 2 +
17 files changed, 596 insertions(+), 46 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml
create mode 100644 Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml
create mode 100644 drivers/phy/renesas/phy-rzg3e-usb3.c
create mode 100644 drivers/usb/host/xhci-rcar-regs.h
create mode 100644 drivers/usb/host/xhci-rzg3e-regs.h
--
2.43.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks
2025-08-20 17:17 [PATCH 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
@ 2025-08-20 17:17 ` Biju
2025-08-20 20:09 ` Conor Dooley
2025-09-02 13:19 ` Geert Uytterhoeven
2025-08-20 17:17 ` [PATCH 02/11] clk: renesas: r9a09g047: Add USB3.0 clocks/resets Biju
1 sibling, 2 replies; 6+ messages in thread
From: Biju @ 2025-08-20 17:17 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-clk, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add definitions for USB3.0 core clocks in the R9A09G047 CPG DT bindings
header file.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
include/dt-bindings/clock/renesas,r9a09g047-cpg.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
index a27132f9a6c8..f165df8a6f5a 100644
--- a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
@@ -20,5 +20,7 @@
#define R9A09G047_SPI_CLK_SPI 9
#define R9A09G047_GBETH_0_CLK_PTP_REF_I 10
#define R9A09G047_GBETH_1_CLK_PTP_REF_I 11
+#define R9A09G047_USB3_0_REF_ALT_CLK_P 12
+#define R9A09G047_USB3_0_CLKCORE 13
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 02/11] clk: renesas: r9a09g047: Add USB3.0 clocks/resets
2025-08-20 17:17 [PATCH 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
2025-08-20 17:17 ` [PATCH 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks Biju
@ 2025-08-20 17:17 ` Biju
2025-09-02 13:27 ` Geert Uytterhoeven
1 sibling, 1 reply; 6+ messages in thread
From: Biju @ 2025-08-20 17:17 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd
Cc: Biju Das, linux-renesas-soc, linux-clk, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add USB3.0 clock and reset entries.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a09g047-cpg.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index afd09b95fb74..e3fed4a3121a 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -16,7 +16,7 @@
enum clk_ids {
/* Core Clock Outputs exported to DT */
- LAST_DT_CORE_CLK = R9A09G047_GBETH_1_CLK_PTP_REF_I,
+ LAST_DT_CORE_CLK = R9A09G047_USB3_0_CLKCORE,
/* External Input Clocks */
CLK_AUDIO_EXTAL,
@@ -181,6 +181,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
CLK_PLLETH_DIV_125_FIX, 1, 1),
DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
CLK_PLLETH_DIV_125_FIX, 1, 1),
+ DEF_FIXED("usb30_ref_alt_clk_p", R9A09G047_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
+ DEF_FIXED("usb30_core_clk", R9A09G047_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1),
};
static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
@@ -276,6 +278,10 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
BUS_MSTOP(8, BIT(4))),
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
BUS_MSTOP(8, BIT(4))),
+ DEF_MOD("usb30_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15,
+ BUS_MSTOP(7, BIT(12))),
+ DEF_MOD("usb30_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
+ BUS_MSTOP(7, BIT(14))),
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
BUS_MSTOP(8, BIT(5)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
@@ -352,6 +358,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
+ DEF_RST(10, 10, 4, 27), /* USB30_ARESETN */
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks
2025-08-20 17:17 ` [PATCH 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks Biju
@ 2025-08-20 20:09 ` Conor Dooley
2025-09-02 13:19 ` Geert Uytterhoeven
1 sibling, 0 replies; 6+ messages in thread
From: Conor Dooley @ 2025-08-20 20:09 UTC (permalink / raw)
To: Biju
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm, Biju Das,
linux-clk, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 54 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks
2025-08-20 17:17 ` [PATCH 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks Biju
2025-08-20 20:09 ` Conor Dooley
@ 2025-09-02 13:19 ` Geert Uytterhoeven
1 sibling, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2025-09-02 13:19 UTC (permalink / raw)
To: Biju
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, Biju Das, linux-clk, devicetree,
linux-kernel, linux-renesas-soc, Prabhakar Mahadev Lad
On Wed, 20 Aug 2025 at 19:18, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add definitions for USB3.0 core clocks in the R9A09G047 CPG DT bindings
> header file.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 02/11] clk: renesas: r9a09g047: Add USB3.0 clocks/resets
2025-08-20 17:17 ` [PATCH 02/11] clk: renesas: r9a09g047: Add USB3.0 clocks/resets Biju
@ 2025-09-02 13:27 ` Geert Uytterhoeven
0 siblings, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2025-09-02 13:27 UTC (permalink / raw)
To: Biju
Cc: Michael Turquette, Stephen Boyd, Biju Das, linux-renesas-soc,
linux-clk, linux-kernel, Prabhakar Mahadev Lad
Hi Biju,
On Wed, 20 Aug 2025 at 19:18, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add USB3.0 clock and reset entries.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/r9a09g047-cpg.c
> +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> @@ -16,7 +16,7 @@
>
> enum clk_ids {
> /* Core Clock Outputs exported to DT */
> - LAST_DT_CORE_CLK = R9A09G047_GBETH_1_CLK_PTP_REF_I,
> + LAST_DT_CORE_CLK = R9A09G047_USB3_0_CLKCORE,
>
> /* External Input Clocks */
> CLK_AUDIO_EXTAL,
> @@ -181,6 +181,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
> CLK_PLLETH_DIV_125_FIX, 1, 1),
> DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
> CLK_PLLETH_DIV_125_FIX, 1, 1),
> + DEF_FIXED("usb30_ref_alt_clk_p", R9A09G047_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
> + DEF_FIXED("usb30_core_clk", R9A09G047_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1),
"usb3_0_..." for both, to match the public define and the clock diagram.
> };
>
> static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
> @@ -276,6 +278,10 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
> BUS_MSTOP(8, BIT(4))),
> DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
> BUS_MSTOP(8, BIT(4))),
> + DEF_MOD("usb30_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15,
> + BUS_MSTOP(7, BIT(12))),
> + DEF_MOD("usb30_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
> + BUS_MSTOP(7, BIT(14))),
"usb3_0_..." for both.
I cannot verify the actual clock bits, but they do lie in the empty
number space. And apparently the censor team forgot to scrub the
MSTOP bits ;-)
> DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
> BUS_MSTOP(8, BIT(5)), 1),
> DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
> @@ -352,6 +358,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
> DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
> DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
> DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
> + DEF_RST(10, 10, 4, 27), /* USB30_ARESETN */
I cannot verify the actual reset bits, but they do lie in the empty
number space.
USB3_0_ARESETN, for consistency with the clocks?
> DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
> DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
> DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-09-02 13:27 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2025-08-20 17:17 [PATCH 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
2025-08-20 17:17 ` [PATCH 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks Biju
2025-08-20 20:09 ` Conor Dooley
2025-09-02 13:19 ` Geert Uytterhoeven
2025-08-20 17:17 ` [PATCH 02/11] clk: renesas: r9a09g047: Add USB3.0 clocks/resets Biju
2025-09-02 13:27 ` Geert Uytterhoeven
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