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From: Laura Nao <laura.nao@collabora.com>
To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com,
	angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de,
	richardcochran@gmail.com
Cc: guangjie.song@mediatek.com, wenst@chromium.org,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
	kernel@collabora.com, "Laura Nao" <laura.nao@collabora.com>,
	"Nícolas F . R . A . Prado" <nfraprado@collabora.com>
Subject: [PATCH v5 04/27] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap()
Date: Fri, 29 Aug 2025 11:18:50 +0200	[thread overview]
Message-ID: <20250829091913.131528-5-laura.nao@collabora.com> (raw)
In-Reply-To: <20250829091913.131528-1-laura.nao@collabora.com>

On MT8196, some clock controllers use a separate regmap for hardware
voting via set/clear/status registers. Add mtk_clk_get_hwv_regmap() to
retrieve this optional regmap, avoiding duplicated lookup code in 
mtk_clk_register_muxes() and mtk_clk_register_gate().

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
---
 drivers/clk/mediatek/clk-mtk.c | 16 ++++++++++++++++
 drivers/clk/mediatek/clk-mtk.h |  1 +
 2 files changed, 17 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index ba1d1c495bc2..19cd27941747 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -685,4 +685,20 @@ void mtk_clk_simple_remove(struct platform_device *pdev)
 }
 EXPORT_SYMBOL_GPL(mtk_clk_simple_remove);
 
+struct regmap *mtk_clk_get_hwv_regmap(struct device_node *node)
+{
+	struct device_node *hwv_node;
+	struct regmap *regmap_hwv;
+
+	hwv_node = of_parse_phandle(node, "mediatek,hardware-voter", 0);
+	if (!hwv_node)
+		return NULL;
+
+	regmap_hwv = device_node_to_regmap(hwv_node);
+	of_node_put(hwv_node);
+
+	return regmap_hwv;
+}
+EXPORT_SYMBOL_GPL(mtk_clk_get_hwv_regmap);
+
 MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index c17fe1c2d732..11962fac43ea 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -245,5 +245,6 @@ int mtk_clk_pdev_probe(struct platform_device *pdev);
 void mtk_clk_pdev_remove(struct platform_device *pdev);
 int mtk_clk_simple_probe(struct platform_device *pdev);
 void mtk_clk_simple_remove(struct platform_device *pdev);
+struct regmap *mtk_clk_get_hwv_regmap(struct device_node *node);
 
 #endif /* __DRV_CLK_MTK_H */
-- 
2.39.5


  parent reply	other threads:[~2025-08-29  9:21 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-29  9:18 [PATCH v5 00/27] Add support for MT8196 clock controllers Laura Nao
2025-08-29  9:18 ` [PATCH v5 01/27] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control Laura Nao
2025-08-29  9:18 ` [PATCH v5 02/27] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC Laura Nao
2025-08-29  9:18 ` [PATCH v5 03/27] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd " Laura Nao
2025-08-29  9:18 ` Laura Nao [this message]
2025-08-29  9:18 ` [PATCH v5 05/27] clk: mediatek: clk-mux: Add ops for mux gates with HW voter " Laura Nao
2025-08-29  9:18 ` [PATCH v5 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct Laura Nao
2025-08-29  9:18 ` [PATCH v5 07/27] clk: mediatek: clk-gate: Add ops for gates with HW voter Laura Nao
2025-08-29  9:18 ` [PATCH v5 08/27] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro Laura Nao
2025-08-29  9:18 ` [PATCH v5 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers Laura Nao
2025-08-29  9:18 ` [PATCH v5 10/27] clk: mediatek: Add MT8196 apmixedsys clock support Laura Nao
2025-08-29  9:18 ` [PATCH v5 11/27] clk: mediatek: Add MT8196 topckgen " Laura Nao
2025-08-29  9:18 ` [PATCH v5 12/27] clk: mediatek: Add MT8196 topckgen2 " Laura Nao
2025-08-29  9:18 ` [PATCH v5 13/27] clk: mediatek: Add MT8196 vlpckgen " Laura Nao
2025-08-29  9:19 ` [PATCH v5 14/27] clk: mediatek: Add MT8196 peripheral " Laura Nao
2025-08-29  9:19 ` [PATCH v5 15/27] clk: mediatek: Add MT8196 ufssys " Laura Nao
2025-08-29  9:19 ` [PATCH v5 16/27] clk: mediatek: Add MT8196 pextpsys " Laura Nao
2025-08-29  9:19 ` [PATCH v5 17/27] clk: mediatek: Add MT8196 I2C " Laura Nao
2025-08-29  9:19 ` [PATCH v5 18/27] clk: mediatek: Add MT8196 mcu " Laura Nao
2025-08-29  9:19 ` [PATCH v5 19/27] clk: mediatek: Add MT8196 mdpsys " Laura Nao
2025-08-29  9:19 ` [PATCH v5 20/27] clk: mediatek: Add MT8196 mfg " Laura Nao
2025-08-29  9:19 ` [PATCH v5 21/27] clk: mediatek: Add MT8196 disp0 " Laura Nao
2025-08-29  9:19 ` [PATCH v5 22/27] clk: mediatek: Add MT8196 disp1 " Laura Nao
2025-08-29  9:19 ` [PATCH v5 23/27] clk: mediatek: Add MT8196 disp-ao " Laura Nao
2025-08-29  9:19 ` [PATCH v5 24/27] clk: mediatek: Add MT8196 ovl0 " Laura Nao
2025-08-29  9:19 ` [PATCH v5 25/27] clk: mediatek: Add MT8196 ovl1 " Laura Nao
2025-08-29  9:19 ` [PATCH v5 26/27] clk: mediatek: Add MT8196 vdecsys " Laura Nao
2025-08-29  9:19 ` [PATCH v5 27/27] clk: mediatek: Add MT8196 vencsys " Laura Nao

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