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[2003:e4:1f1c:4d00:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-3e7607cd43csm12396259f8f.29.2025.09.13.23.40.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Sep 2025 23:40:08 -0700 (PDT) From: Thierry Reding To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [GIT PULL] clk: tegra: Changes for v6.18-rc1 Date: Sun, 14 Sep 2025 08:40:04 +0200 Message-ID: <20250914064006.90225-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.50.0 Content-Type: text/plain; charset="utf-8" Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Mike, Stephen, The following changes since commit 04f27a0fda6b6be104531eeb95d07ef1b3a72af8: dt-bindings: arm: tegra: Add ASUS TF101G and SL101 (2025-09-11 18:28:57 +0200) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/for-6.18-clk for you to fetch changes up to 5aba939e80f439c1a67adb6d9cae23cc72db7ef9: clk: tegra: dfll: Add CVB tables for Tegra114 (2025-09-14 08:23:28 +0200) This depends on the dt-bindings branch because of the DT header file that the driver includes. Thanks, Thierry ---------------------------------------------------------------- clk: tegra: Changes for v6.18-rc1 Add DFLL support on Tegra114. This is quite similar to the existing Tegra124 support and most of the code can be reused, except for the CVB frequency tables. ---------------------------------------------------------------- Svyatoslav Ryhel (2): clk: tegra: Add DFLL DVCO reset control for Tegra114 clk: tegra: dfll: Add CVB tables for Tegra114 Thierry Reding (1): Merge branch 'for-6.18/dt-bindings' into for-6.18/clk drivers/clk/tegra/Kconfig | 2 +- drivers/clk/tegra/clk-tegra114.c | 30 +++++- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 158 ++++++++++++++++++++++++----- drivers/clk/tegra/clk.h | 2 - 4 files changed, 158 insertions(+), 34 deletions(-)