[GIT PULL v2] ARM: microchip: clk for 6.18 #1

nicolas.ferre
2025-09-17T18:22:40Z

From: Nicolas Ferre <nicolas.ferre@microchip.com>

Dear clock maintainers,

Here are the first clk changes for 6.18.
I don't think they have conflict with changes for the deprecated round_rate()
to determine_rate() topic.
In this v2, I address the issue highlighted by 0-day robot: build issue. I
added a patch that is already included as well in an pull-request to arm-soc:
https://lore.kernel.org/linux-arm-kernel/20250916150328.27015-1-nicolas.ferre@microchip.com/

v1 --> v2:
- addition of the patch "ARM: at91: pm: save and restore ACR during PLL
disable/enable" as the first patch of the series to avoid build error if clk
tree is merged before arm-soc. Branch bisect-able. Exact same patch
in both trees.
- a new tag (clk-microchip-6.18-2) is created and deployed for this
v2 pull-request

Thanks, best regards,
Nicolas

The following changes since commit 8f5ae30d69d7543eee0d70083daf4de8fe15d585:

Linux 6.17-rc1 (2025-08-10 19:41:16 +0300)

are available in the Git repository at:

git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git tags/clk-microchip-6.18-2

for you to fetch changes up to 652b08afba69d5d26fe91098eb832b1bcc0f91c2:

ARM: at91: remove default values for PMC_PLL_ACR (2025-09-17 19:15:32 +0200)

----------------------------------------------------------------
Microchip clock updates for v6.18

This update includes:
- add one clock for sam9x75
- new meaning for MCR register field in clk-master
- use force-write to PLL update register to ensure
reliable programming sequence
- update Analog Control Register (ACR) management to accommodate
differences across SoCs.
- ACR management dependency with one ARM PM patch added beforehand

----------------------------------------------------------------
Balamanikandan Gunasundar (1):
clk: at91: sam9x7: Add peripheral clock id for pmecc

Cristian Birsan (2):
clk: at91: add ACR in all PLL settings
ARM: at91: remove default values for PMC_PLL_ACR

Nicolas Ferre (2):
ARM: at91: pm: save and restore ACR during PLL disable/enable
clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register

Ryan Wanner (1):
clk: at91: clk-master: Add check for divide by 3

arch/arm/mach-at91/pm_suspend.S | 8 +++-
drivers/clk/at91/clk-master.c | 3 ++
drivers/clk/at91/clk-sam9x60-pll.c | 82 +++++++++++++++++------------------
drivers/clk/at91/pmc.h | 1 +
drivers/clk/at91/sam9x60.c | 2 +
drivers/clk/at91/sam9x7.c | 6 +++
drivers/clk/at91/sama7d65.c | 4 ++
drivers/clk/at91/sama7g5.c | 2 +
include/linux/clk/at91_pmc.h | 2 -
9 files changed, 66 insertions(+), 44 deletions(-)

--
Nicolas Ferre