Re: [PATCH v3 2/2] drm: renesas: rz-du: Set DSI divider based on target MIPI device

[kernel test robot <lkp@intel.com>]

Hi Chris,

kernel test robot noticed the following build errors:

[auto build test ERROR on clk/clk-next]
[also build test ERROR on geert-renesas-drivers/renesas-clk sunxi/sunxi/for-next linus/master v6.18-rc2 next-20251023]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Chris-Brandt/clk-renesas-rzg2l-Remove-DSI-clock-rate-restrictions/20251023-080220
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
patch link:    https://lore.kernel.org/r/20251022235903.1091453-3-chris.brandt%40renesas.com
patch subject: [PATCH v3 2/2] drm: renesas: rz-du: Set DSI divider based on target MIPI device
config: powerpc-randconfig-002-20251023 (https://download.01.org/0day-ci/archive/20251024/202510240111.DvVTqUEp-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project e1ae12640102fd2b05bc567243580f90acb1135f)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251024/202510240111.DvVTqUEp-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202510240111.DvVTqUEp-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c:751:31: error: called object type 'void *' is not a function or function pointer
     751 |         rzg2l_cpg_dsi_div_set_divider(mipi_dsi_pixel_format_to_bpp(dsi->format) / dsi->lanes,
         |         ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^
   1 error generated.

Kconfig warnings: (for reference only)
   WARNING: unmet direct dependencies detected for HOTPLUG_CPU
   Depends on [n]: SMP [=y] && (PPC_PSERIES [=n] || PPC_PMAC [=n] || PPC_POWERNV [=n] || FSL_SOC_BOOKE [=n])
   Selected by [y]:
   - PM_SLEEP_SMP [=y] && SMP [=y] && (ARCH_SUSPEND_POSSIBLE [=y] || ARCH_HIBERNATION_POSSIBLE [=y]) && PM_SLEEP [=y]


vim +751 drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c

   687	
   688	/* -----------------------------------------------------------------------------
   689	 * Host setting
   690	 */
   691	
   692	static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host,
   693					      struct mipi_dsi_device *device)
   694	{
   695		struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host);
   696		int ret;
   697	
   698		if (device->lanes > dsi->num_data_lanes) {
   699			dev_err(dsi->dev,
   700				"Number of lines of device (%u) exceeds host (%u)\n",
   701				device->lanes, dsi->num_data_lanes);
   702			return -EINVAL;
   703		}
   704	
   705		switch (mipi_dsi_pixel_format_to_bpp(device->format)) {
   706		case 24:
   707			break;
   708		case 18:
   709			break;
   710		case 16:
   711			if (!(dsi->info->features & RZ_MIPI_DSI_FEATURE_16BPP)) {
   712				dev_err(dsi->dev, "Unsupported format 0x%04x\n",
   713					device->format);
   714				return -EINVAL;
   715			}
   716			break;
   717		default:
   718			dev_err(dsi->dev, "Unsupported format 0x%04x\n", device->format);
   719			return -EINVAL;
   720		}
   721	
   722		dsi->lanes = device->lanes;
   723		dsi->format = device->format;
   724		dsi->mode_flags = device->mode_flags;
   725	
   726		dsi->next_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node,
   727							  1, 0);
   728		if (IS_ERR(dsi->next_bridge)) {
   729			ret = PTR_ERR(dsi->next_bridge);
   730			dev_err(dsi->dev, "failed to get next bridge: %d\n", ret);
   731			return ret;
   732		}
   733	
   734		drm_bridge_add(&dsi->bridge);
   735	
   736		/*
   737		 * Report required division ratio setting for the MIPI clock dividers.
   738		 * Assume the default clock source is FOUTPOSTDIV (PLL/2) being fed to the DSI-PHY, but also
   739		 * the DSI-PHY must be 16x the MIPI-DSI HS clock.
   740		 *
   741		 * pllclk / 2 = vclk * DSI divider
   742		 * pllclk = vclk * DSI divider * 2
   743		 *
   744		 * hsclk = (vclk * DSI divider * 2) / 16
   745		 *
   746		 * vclk * bpp = hsclk * 8 * num_lanes
   747		 * vclk * bpp = ((vclk * DSI divider * 2) / 16) * 8 * num_lanes
   748		 *   which simplifies to...
   749		 * DSI divider = bpp / num_lanes
   750		 */
 > 751		rzg2l_cpg_dsi_div_set_divider(mipi_dsi_pixel_format_to_bpp(dsi->format) / dsi->lanes,
   752					      PLL5_TARGET_DSI);
   753	
   754		return 0;
   755	}
   756	

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