[PATCH v3 15/21] clk: mediatek: Add MT8189 mfg clock support

irving.ch.lin
2025-11-06T12:43:53Z

Add support for the MT8189 mfg clock controller,
which provides clock gate control for the GPU.

Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
---
drivers/clk/mediatek/Kconfig | 11 ++++++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8189-mfg.c | 56 +++++++++++++++++++++++++++
3 files changed, 68 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8189-mfg.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index ef962f5816a8..316d010b503a 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -906,6 +906,17 @@ config COMMON_CLK_MT8189_MDPSYS
chipset, ensuring that the display system operates efficiently and
effectively.

+config COMMON_CLK_MT8189_MFG
+ tristate "Clock driver for MediaTek MT8189 mfg"
+ depends on COMMON_CLK_MT8189
+ default COMMON_CLK_MT8189
+ help
+ Enable this option to support the manufacturing clocks for the MediaTek
+ MT8189 chipset. This driver provides the necessary clock framework
+ integration for manufacturing tests and operations that are specific to
+ the MT8189 chipset. Enabling this will allow the manufacturing mode of
+ the chipset to function correctly with the appropriate clock settings.
+
config COMMON_CLK_MT8192
tristate "Clock driver for MediaTek MT8192"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 9b23e4c5e019..07f11760cf68 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -132,6 +132,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) += clk-mt8189-dvfsrc.o
obj-$(CONFIG_COMMON_CLK_MT8189_IIC) += clk-mt8189-iic.o
obj-$(CONFIG_COMMON_CLK_MT8189_IMG) += clk-mt8189-img.o
obj-$(CONFIG_COMMON_CLK_MT8189_MDPSYS) += clk-mt8189-mdpsys.o
+obj-$(CONFIG_COMMON_CLK_MT8189_MFG) += clk-mt8189-mfg.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-mfg.c b/drivers/clk/mediatek/clk-mt8189-mfg.c
new file mode 100644
index 000000000000..d4c20118247f
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-mfg.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Qiqi Wang <qiqi.wang@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+
+static const struct mtk_gate_regs mfg_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_MFG(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mfg_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ .flags = CLK_OPS_PARENT_ENABLE | CLK_IGNORE_UNUSED, \
+ }
+
+static const struct mtk_gate mfg_clks[] = {
+ GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel_mfgpll", 0),
+};
+
+static const struct mtk_clk_desc mfg_mcd = {
+ .clks = mfg_clks,
+ .num_clks = ARRAY_SIZE(mfg_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8189_mfg[] = {
+ { .compatible = "mediatek,mt8189-mfgcfg", .data = &mfg_mcd },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8189_mfg_drv = {
+ .probe = mtk_clk_simple_probe,
+ .driver = {
+ .name = "clk-mt8189-mfg",
+ .of_match_table = of_match_clk_mt8189_mfg,
+ },
+};
+
+module_platform_driver(clk_mt8189_mfg_drv);
+MODULE_LICENSE("GPL");
--
2.45.2