[PATCH v3 03/21] clk: mediatek: fix mfg mux issue

irving.ch.lin
2025-11-06T12:43:44Z

MFG mux design is different for MTK SoCs,
For MT8189, we need to enable parent first
to garentee parent clock stable.

Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
---
drivers/clk/mediatek/clk-mux.c | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c
index c5af6dc078a3..15309c7dbbfb 100644
--- a/drivers/clk/mediatek/clk-mux.c
+++ b/drivers/clk/mediatek/clk-mux.c
@@ -414,16 +414,20 @@ static int mtk_clk_mux_notifier_cb(struct notifier_block *nb,
struct clk_notifier_data *data = _data;
struct clk_hw *hw = __clk_get_hw(data->clk);
struct mtk_mux_nb *mux_nb = to_mtk_mux_nb(nb);
+ struct clk_hw *p_hw = clk_hw_get_parent_by_index(hw,
+ mux_nb->bypass_index);
int ret = 0;

switch (event) {
case PRE_RATE_CHANGE:
+ clk_prepare_enable(p_hw->clk);
mux_nb->original_index = mux_nb->ops->get_parent(hw);
ret = mux_nb->ops->set_parent(hw, mux_nb->bypass_index);
break;
case POST_RATE_CHANGE:
case ABORT_RATE_CHANGE:
ret = mux_nb->ops->set_parent(hw, mux_nb->original_index);
+ clk_disable_unprepare(p_hw->clk);
break;
}

--
2.45.2