[PATCH v5 2/4] arm64: dts: exynos: gs101: add samsung,sysreg property to CMU nodes

Peter Griffin
2025-11-14T14:17:04Z

With the exception of cmu_top, each CMU has a corresponding sysreg bank
that contains the BUSCOMPONENT_DRCG_EN and optional MEMCLK registers.
The BUSCOMPONENT_DRCG_EN register enables dynamic root clock gating of
bus components and MEMCLK gates the sram clock.

Now the clock driver supports automatic clock mode, provide the
samsung,sysreg property so the driver can enable dynamic root clock
gating of bus components and gate sram clock.

Note without the property specified the driver simply falls back to
previous behaviour of not configuring these registers so it is not an ABI
break.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
Changes in v4:
- Update commit message (Peter)
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index d06d1d05f36408137a8acd98e43d48ea7d4f4292..c39ca4c4508f046ca16ae86be42468c7245561b8 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -578,6 +578,7 @@ cmu_misc: clock-controller@10010000 {
clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>,
<&cmu_top CLK_DOUT_CMU_MISC_SSS>;
clock-names = "bus", "sss";
+ samsung,sysreg = <&sysreg_misc>;
};

sysreg_misc: syscon@10030000 {
@@ -662,6 +663,7 @@ cmu_peric0: clock-controller@10800000 {
<&cmu_top CLK_DOUT_CMU_PERIC0_BUS>,
<&cmu_top CLK_DOUT_CMU_PERIC0_IP>;
clock-names = "oscclk", "bus", "ip";
+ samsung,sysreg = <&sysreg_peric0>;
};

sysreg_peric0: syscon@10820000 {
@@ -1208,6 +1210,7 @@ cmu_peric1: clock-controller@10c00000 {
<&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
<&cmu_top CLK_DOUT_CMU_PERIC1_IP>;
clock-names = "oscclk", "bus", "ip";
+ samsung,sysreg = <&sysreg_peric1>;
};

sysreg_peric1: syscon@10c20000 {
@@ -1566,6 +1569,7 @@ cmu_hsi0: clock-controller@11000000 {
<&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>;
clock-names = "oscclk", "bus", "dpgtc", "usb31drd",
"usbdpdbg";
+ samsung,sysreg = <&sysreg_hsi0>;
};

sysreg_hsi0: syscon@11020000 {
@@ -1637,6 +1641,7 @@ cmu_hsi2: clock-controller@14400000 {
<&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
<&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
+ samsung,sysreg = <&sysreg_hsi2>;
};

sysreg_hsi2: syscon@14420000 {
@@ -1697,6 +1702,7 @@ cmu_apm: clock-controller@17400000 {

clocks = <&ext_24_5m>;
clock-names = "oscclk";
+ samsung,sysreg = <&sysreg_apm>;
};

sysreg_apm: syscon@17420000 {

--
2.52.0.rc1.455.g30608eb744-goog