On Thu, Jan 29, 2026 at 02:07:29PM +0000, Fabrizio Castro wrote:
> When the bindings for the Renesas RZ/V2H(P) SoC were factored
> out IP WDT0 was selected for the example, however the HW user
> manual states that only IP WDT1 can be used by Linux.
> 
> This commit is part of a series that removes WDT{0,2,3} support
> from the kernel, therefore the example from the bindings has
> lost its meaning.
> 
> Update the example accordingly.
> 
> Fixes: fcba2855251f ("dt-bindings: watchdog: factor out RZ/V2H(P) watchdog")

Given this is an example, I don't think a fixes tag is appropriate here.

> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> ---
>  .../bindings/watchdog/renesas,r9a09g057-wdt.yaml          | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml
> index 099200c4f136..975c5aa4d747 100644
> --- a/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml
> @@ -89,11 +89,11 @@ examples:
>    - |
>      #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
>  
> -    watchdog@11c00400 {
> +    watchdog@14400000 {
>              compatible = "renesas,r9a09g057-wdt";
> -            reg = <0x11c00400 0x400>;
> -            clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
> +            reg = <0x14400000 0x400>;
> +            clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>;
>              clock-names = "pclk", "oscclk";
> -            resets = <&cpg 0x75>;
> +            resets = <&cpg 0x76>;
>              power-domains = <&cpg>;
>      };
> -- 
> 2.34.1
>