From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-182.mta0.migadu.com (out-182.mta0.migadu.com [91.218.175.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2F7726A0DD for ; Sat, 28 Feb 2026 20:47:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.182 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772311643; cv=none; b=VZC0tdtPJXtWn4mLCJS34INdx/1/fMVE2IBoMGH5NjC6lOQgc5ZfJGtuaLNk88eCV77MA7ljQRIt77QY90eHEc5OLIZktgnVJlwswEKBfozqi1VyN9hmzRujCoIRr9WpxbprTcoQLBAMpn6Anfdim0lcAYVMjbmFlChsboZ/pow= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772311643; c=relaxed/simple; bh=q2B2Ljgs5Ws079qJ03QnY0pPOMhYQcO46xILryodcrg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=J95zaVZcLpSZztUj6MOuu8OUr+pwfL110jX7zlVePWDTxpaZ19Fvp8guTHw82R7nSmJyyPimP5VMhuSeH4WsGExAb0L5nMHg0k0ZxpILm15z12t5oiK1sNa0SIkXSC55gielszjnES0EWNmmCH0fCaRQa1XFUJsL0y301exlG/Q= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=NBK2DHWQ; arc=none smtp.client-ip=91.218.175.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="NBK2DHWQ" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1772311639; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fZ4YCYZelX6xrgCcTEYuiYxr56vs8RNwPeKvzB3MVZM=; b=NBK2DHWQWSYe0nAGnvxSHCMvur5X+VTXIVhTLbIL8H0awrd1rKSBub5hQOdsQCq7QRlC78 iN2H8Szoh6ccacMOYeOfYEwWbXTnR3enb/faANe5Xl6wTUavzLJk1+wKbl93+BMh1BkeUf VzYgN1yd/x15/UdIkIDsQF+HCntqPTlXPbnfOWZR0HI/5jzov+4ANRBuj7iG2ZIsFc/RIR NWHQTOtO6LT0HsTGQI8xfW/E8vVEwmZ/V4XPHd04HMVowTMO5do0sN/T9jWTQ+1jILTfAi AZj+i0P9DaXAYTbVUmNITPYSXmSEwxvlvrDZwUQ0Gn0hdrv689b1IziXTAcGHw== From: Val Packett To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Adam Skladowski Cc: Val Packett , linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/6] dt-bindings: clock: qcom,sm6115-dispcc: Define MDSS resets Date: Sat, 28 Feb 2026 17:41:27 -0300 Message-ID: <20260228204638.11705-2-val@packett.cool> In-Reply-To: <20260228204638.11705-1-val@packett.cool> References: <20260228204638.11705-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT Add the missing defines for MDSS resets, which are necessary to reset the display subsystem in order to avoid issues caused by state left over from the bootloader. While here, align comment style with other SoCs. Fixes: 38557c6fc077 ("dt-bindings: clock: add QCOM SM6115 display clock bindings") Signed-off-by: Val Packett --- include/dt-bindings/clock/qcom,sm6115-dispcc.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/clock/qcom,sm6115-dispcc.h b/include/dt-bindings/clock/qcom,sm6115-dispcc.h index d1a6c45b5029..ab8d312ade37 100644 --- a/include/dt-bindings/clock/qcom,sm6115-dispcc.h +++ b/include/dt-bindings/clock/qcom,sm6115-dispcc.h @@ -6,7 +6,7 @@ #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H -/* DISP_CC clocks */ +/* Clocks */ #define DISP_CC_PLL0 0 #define DISP_CC_PLL0_OUT_MAIN 1 #define DISP_CC_MDSS_AHB_CLK 2 @@ -30,7 +30,10 @@ #define DISP_CC_SLEEP_CLK 20 #define DISP_CC_SLEEP_CLK_SRC 21 -/* DISP_CC GDSCR */ +/* Resets */ +#define DISP_CC_MDSS_CORE_BCR 0 + +/* GDSCs */ #define MDSS_GDSC 0 #endif -- 2.52.0