From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55816279355; Sun, 1 Mar 2026 11:54:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772366050; cv=none; b=EFHFLnds3UNp0oIPKZsOrnrBA9OcgO3EEM2IsCLBDPxpzo8irqbGclbF0Z+d1FaEBVJtAV+9OLIdraNlPKnOAyLLLbzhfpQUiqNy7OQF6SCGrL1vbzzCGi0rbSH8Kx3VxL04j4hTen/o5gH0ds8br0jAgrzHAVdu28FFuGqX4CU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772366050; c=relaxed/simple; bh=dDKVwRGZph9yuhRFeF4vHmj71PEVAlDKHpsemp9Xla4=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=gWvLoTMl3ri4bAiH7m/GH1o9ijzJRazjFuwyP4hTDYJY0Yor0qSw9pmYzAsXZGA4AhA6grYal/Xfmdcomdbz10sYgQBdARI+yOUCw3NeUf+o61n7hF7HJCzRmfR8tObHb8VmLaCuJ3DKLiGZSam2tBf7f9TedDW+5Fsk7+1q6bM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YtNpT2hA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YtNpT2hA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 96CFAC116C6; Sun, 1 Mar 2026 11:54:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772366050; bh=dDKVwRGZph9yuhRFeF4vHmj71PEVAlDKHpsemp9Xla4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=YtNpT2hATp5+LiJ4WofhOnhUujbuazYLFo7+p337b2DeLMkPmkY0DG6eFZPaUhrm/ uyr51Jn8oENGAFCkwocxeIU4pivtYuOPOr7Ef/pzOPxUIigm/2zq7WM6eOeGZ7pHdi sia7r1GLHNwsDu35uuLOUTXPIi4oDbbTV7FkwD79fuqPTzsvz9wNUnpnaMmdrruxvz uR8xUCffkSkrvmoh61h8UwtQt6qO75ULG/X33Z8EZumgXcXmxrYoILCG78Ghn1jmxW XJ+eWrxmmD98owRLfmtTa1YgZoaEknbmjD0MxjPq0GVtK1TNobdYHVzvlhJ2MpPb+S jzLxqW7J7sC0g== Date: Sun, 1 Mar 2026 12:54:07 +0100 From: Krzysztof Kozlowski To: Val Packett Cc: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Adam Skladowski , linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Subject: Re: [PATCH v2 3/6] clk: qcom: dispcc-sm6115: Add missing MDSS resets Message-ID: <20260301-arcane-augmented-gazelle-c3cf4c@quoll> References: <20260228204638.11705-1-val@packett.cool> <20260228204638.11705-4-val@packett.cool> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20260228204638.11705-4-val@packett.cool> On Sat, Feb 28, 2026 at 05:41:29PM -0300, Val Packett wrote: > The MDSS resets were left undescribed. Add them to allow resetting the > display subsystem, which is necessary to avoid issues caused by state > left over from the bootloader on various platforms. > > Fixes: 9b518788631c ("clk: qcom: Add display clock controller driver for SM6115") Not a bug being fixed here. Best regards, Krzysztof