From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 565F438B122; Tue, 10 Mar 2026 17:33:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773163988; cv=none; b=KhOSE6x1S+CReDhxYR9tPT9Ea1GQCl4lmO3MBMCyv5PD4/nvGveSivif+I1zV4ph2irrdCnfhyEkgegRfASQPuY4m0OnspgsvvypAsGE04sgD72zL7/wZJx0aL3ennLZRXTeHeBC4C7mv09JR3O+6E6xmL0bkgcyEY2GXhasuso= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773163988; c=relaxed/simple; bh=tKpuYF4SZR5lkozkhfn8XfbK2UfIoUqnYkKbMoA133c=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version:Content-Type; b=LGm7PRsk5OcAA7N0ctYTSZgft/QPQC+TLc1M96hbUyp5KLHtI1XdPtbz+5l8VwtH/lAPic0hoSOL2yxlOYKNCwybmI9FN41U0i2Ns+JwHfMfi27fqCRTNrbZ5Iwqf22VYN/POMXDsx7qdRV/DQcvGrFxStBOlmSN1fU4bm84z7s= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=zHPWFiF/; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="zHPWFiF/" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id BA68A4E425F2; Tue, 10 Mar 2026 17:33:02 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 8591060002; Tue, 10 Mar 2026 17:33:02 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 5FF741036891C; Tue, 10 Mar 2026 18:32:57 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773163981; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding; bh=GV/3yyZ/K5WPAlPx10KVrpjD34hKneXHwsacFm5yDNk=; b=zHPWFiF/U1qmeqt696VrBIHDjnldCPoHr6tmMQwbmcp53DwLjD6Zgpv9BTCRz2FPTTYA5h c/vjHW9wRtidn0qowanw4btRtvhiQzyYeiCQvH6QGZNK8pmv3ZUvFgsqaTmBezeAfeGynd tfclbhTFoadOd3XyXyrTvf3hgUZoL3eFJ7Q1PQqIy2cwqaFBCewQT/cuirN5oYvE/SEg3y k5/z5qC9QNn+KwtCHXVVI5GfIQGrCzpycusii2Mst4K840wue0GosU0jng5deGPmsF+OGx j5df5QrqotqBdPQtDiYb0dAds082NviHpmnkEGiau3xRwpikI8is+eXo+n7nwA== From: "Herve Codina (Schneider Electric)" To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Magnus Damm , Wolfram Sang Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Pascal Eberhard , Miquel Raynal , Thomas Petazzoni , "Herve Codina (Schneider Electric)" Subject: [PATCH 0/5] watchdog: rzn1: Add support for direct hardware reset Date: Tue, 10 Mar 2026 18:32:41 +0100 Message-ID: <20260310173249.161354-1-herve.codina@bootlin.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 Hi, The current watchdog driver handling wachdogs of the RZ/N1 SoCs is based on interrupt only to perform the reset. On the watchdog timeout, an interrupt is triggered and the software initiates the reset. The watchdogs available in the RZ/N1 SoCs can directly perform an hardware reset using their dedicated reset line. On timeout, the watchdog also asserts its dedicated reset line. This reset line is connected to the reset controller (part of sysctrl) and, if this line is enabled as a possible reset source at the reset controller level, it initiates a system reset. This series adds support for this feature allowing watchdogs to directly reset the system with any software needs when a watchdog timeout occurs. The first two patches are minor fixes and improvements without changing the current functional behavior. Patches 3 to 5 add support for the feature adding: - The reset line description in the RZ/N1 watchdog binding, - A new helper at sysctrl level (sysctrl is handled by the clock driver in RZ/N1) to enable watchdog reset sources, - The support itself in the watchdog driver putting everything together. Best regards, Hervé Herve Codina (Schneider Electric) (5): watchdog: rzn1: Fix reverse xmas tree declaration watchdog: rzn1: Use dev_err_probe() dt-bindings: watchdog: renesas,rzn1-wdt: Document the reset line clk: renesas: r9a06g032: Introduce a helper to set rsten register watchdog: rzn1: Add support for direct hardware reset .../bindings/watchdog/renesas,rzn1-wdt.yaml | 22 +++++++ drivers/clk/renesas/r9a06g032-clocks.c | 32 ++++++++++ drivers/watchdog/rzn1_wdt.c | 63 ++++++++++++++----- .../dt-bindings/watchdog/renesas,rzn1-wdt.h | 16 +++++ include/linux/soc/renesas/r9a06g032-sysctrl.h | 12 ++++ 5 files changed, 131 insertions(+), 14 deletions(-) create mode 100644 include/dt-bindings/watchdog/renesas,rzn1-wdt.h -- 2.53.0