[PATCH v3 0/1] watchdog: rzn1: Add support for direct hardware reset

[PATCH v3 0/1] watchdog: rzn1: Add support for direct hardware reset

[Herve Codina (Schneider Electric)]

Hi,

The current watchdog driver handling wachdogs of the RZ/N1 SoCs is based
on interrupt only to perform the reset. On the watchdog timeout, an
interrupt is triggered and the software initiates the reset.

The watchdogs available in the RZ/N1 SoCs can directly perform an
hardware reset using their dedicated reset line.

On timeout, the watchdog also asserts its dedicated reset line. This
reset line is connected to the reset controller (part of sysctrl) and,
if this line is enabled as a possible reset source at the reset
controller level, it initiates a system reset.

This series adds support for this feature allowing watchdogs to directly
reset the system without any software needs when a watchdog timeout
occurs.

Compare to previous iteration, in this v3 series patches 1 and 2 have
been removed (sent in a dedicated series) and a swap in OR-ed value
lines has been done.

Best regards,
Hervé

Changes v2 -> v3
  v2: https://lore.kernel.org/all/20260313092417.294356-1-herve.codina@bootlin.com/

  Patches 1 and 2 in v2 removed
    Those patches have been sent in a dedicated series.
    https://lore.kernel.org/all/20260324114849.242755-1-herve.codina@bootlin.com/

  Patch 1 (patch 3 in v2)
    Swap OR-ed value lines in order to have MRESET_EN at the end.
    Add 'Reviewed-by: Wolfram Sang'
    Add 'Tested-by: Wolfram Sang'

Changes v1 -> v2:
  v1: https://lore.kernel.org/lkml/20260310173249.161354-1-herve.codina@bootlin.com/

  Patch 1 and 2:
    No changes

  Patch 3 (new in v2):
    Unconditionally enable watchdog reset sources

  Patch 3, 4 and 5 in v1:
    Removed

Herve Codina (Schneider Electric) (1):
  clk: renesas: r9a06g032: Enable watchdog reset sources

 drivers/clk/renesas/r9a06g032-clocks.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

-- 
2.53.0

[PATCH v3 1/1] clk: renesas: r9a06g032: Enable watchdog reset sources

[Herve Codina (Schneider Electric)]

The watchdog timeout is signaled using an interrupt and, on this
interrupt, a software initiated reset is performed.

This software initiated reset performs, in the end, a hardware system
reset using SWRST_REQ of RSTCTRL register.

The watchdog itself is able to control directly the hardware system
reset without any operation done by the interrupt handler. This feature
allows the watchdog to not depend on the software to reset the system
when a watchdog timeout occurs.

Indeed, when the watchdog timeout occurs, the watchdog requests a system
reset using its own hardware dedicated line but this reset source is
disabled at the reset controller level.

To benefit of this feature and be robust against software issues, enable
watchdogs reset sources.

Suggested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/clk/renesas/r9a06g032-clocks.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c
index 7407a4183a6c..2bed88e09ce6 100644
--- a/drivers/clk/renesas/r9a06g032-clocks.c
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -1342,8 +1342,9 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev)
 	/* Clear potentially pending resets */
 	writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1,
 	       clocks->reg + R9A06G032_SYSCTRL_RSTCTRL);
-	/* Allow software reset */
-	writel(R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN,
+	/* Allow watchdogs and software resets */
+	writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1 |
+	       R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN,
 	       clocks->reg + R9A06G032_SYSCTRL_RSTEN);
 
 	error = devm_register_sys_off_handler(dev, SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,
-- 
2.53.0

Re: [PATCH v3 1/1] clk: renesas: r9a06g032: Enable watchdog reset sources

[Geert Uytterhoeven]

On Tue, 24 Mar 2026 at 13:04, Herve Codina (Schneider Electric)
<herve.codina@bootlin.com> wrote:
> The watchdog timeout is signaled using an interrupt and, on this
> interrupt, a software initiated reset is performed.
>
> This software initiated reset performs, in the end, a hardware system
> reset using SWRST_REQ of RSTCTRL register.
>
> The watchdog itself is able to control directly the hardware system
> reset without any operation done by the interrupt handler. This feature
> allows the watchdog to not depend on the software to reset the system
> when a watchdog timeout occurs.
>
> Indeed, when the watchdog timeout occurs, the watchdog requests a system
> reset using its own hardware dedicated line but this reset source is
> disabled at the reset controller level.
>
> To benefit of this feature and be robust against software issues, enable
> watchdogs reset sources.
>
> Suggested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v7.1.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds