Re: [PATCH v4 5/6] clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()

Brian Masney
2026-04-07T19:03:26Z

Hi Marek,

On Mon, Apr 06, 2026 at 11:49:45PM +0200, Marek Vasut wrote:
> Create helper function fsl_sai_clk_register() to set up and register
> SAI clock. Rename BCLK specific struct fsl_sai_clk members with bclk_
> prefix. Use of_node_full_name(dev->of_node) and clock name to register
> uniquely named clock. This is done in preparation for the follow up
> patch, which adds MCLK support.
>
> Signed-off-by: Marek Vasut <marex@nabladev.com>
> ---
> Cc: Brian Masney <bmasney@redhat.com>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Michael Walle <michael@walle.cc>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> ---
> V4: New patch
> ---
> drivers/clk/clk-fsl-sai.c | 78 ++++++++++++++++++++++++++-------------
> 1 file changed, 53 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
> index 2a68e32c3167b..7ec9a4f22735c 100644
> --- a/drivers/clk/clk-fsl-sai.c
> +++ b/drivers/clk/clk-fsl-sai.c
> @@ -21,8 +21,9 @@
> #define CR2_DIV_WIDTH 8
>
> struct fsl_sai_clk {
> - struct clk_divider div;
> - struct clk_gate gate;
> + struct clk_divider bclk_div;
> + struct clk_gate bclk_gate;
> + struct clk_hw *bclk_hw;
> spinlock_t lock;
> };
>
> @@ -30,15 +31,57 @@ struct fsl_sai_data {
> unsigned int offset; /* Register offset */
> };
>
> +static int fsl_sai_clk_register(struct device *dev, void __iomem *base,
> + spinlock_t *lock, struct clk_divider *div,
> + struct clk_gate *gate, struct clk_hw **hw,
> + const int gate_bit, const int dir_bit,
> + const int div_reg, char *name)
> +{
> + const struct fsl_sai_data *data = device_get_match_data(dev);
> + struct clk_parent_data pdata = { .index = 0 };
> + struct clk_hw *chw;
> + char *cname;
> +
> + gate->reg = base + data->offset + I2S_CSR;
> + gate->bit_idx = gate_bit;
> + gate->lock = lock;
> +
> + div->reg = base + div_reg;
> + div->shift = CR2_DIV_SHIFT;
> + div->width = CR2_DIV_WIDTH;
> + div->lock = lock;
> +
> + cname = devm_kasprintf(dev, GFP_KERNEL, "%s.%s",
> + of_node_full_name(dev->of_node), name);
> + if (!cname)
> + return -ENOMEM;
> +
> + chw = devm_clk_hw_register_composite_pdata(dev, cname,
> + &pdata, 1, NULL, NULL,
> + &div->hw,
> + &clk_divider_ops,
> + &gate->hw,
> + &clk_gate_ops,
> + CLK_SET_RATE_GATE);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);

s/hw/chw/ on the two lines above.

> +
> + *hw = chw;
> +
> + /* Set clock direction */
> + writel(dir_bit, base + div_reg);

The previous behavior of the code was to call writel() and then register
the clk. This flips it. Just to be sure no regressions are introduced,
should we keep the old behavior?

> +
> + return 0;
> +}
> +
> static int fsl_sai_clk_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> const struct fsl_sai_data *data = device_get_match_data(dev);
> struct fsl_sai_clk *sai_clk;
> - struct clk_parent_data pdata = { .index = 0 };
> struct clk *clk_bus;
> void __iomem *base;
> - struct clk_hw *hw;
> + int ret;
>
> sai_clk = devm_kzalloc(dev, sizeof(*sai_clk), GFP_KERNEL);
> if (!sai_clk)
> @@ -54,27 +97,12 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
>
> spin_lock_init(&sai_clk->lock);
>
> - sai_clk->gate.reg = base + data->offset + I2S_CSR;
> - sai_clk->gate.bit_idx = CSR_BCE_BIT;
> - sai_clk->gate.lock = &sai_clk->lock;
> -
> - sai_clk->div.reg = base + data->offset + I2S_CR2;
> - sai_clk->div.shift = CR2_DIV_SHIFT;
> - sai_clk->div.width = CR2_DIV_WIDTH;
> - sai_clk->div.lock = &sai_clk->lock;
> -
> - /* set clock direction, we are the BCLK master */
> - writel(CR2_BCD, base + data->offset + I2S_CR2);
> -
> - hw = devm_clk_hw_register_composite_pdata(dev, dev->of_node->name,
> - &pdata, 1, NULL, NULL,
> - &sai_clk->div.hw,
> - &clk_divider_ops,
> - &sai_clk->gate.hw,
> - &clk_gate_ops,
> - CLK_SET_RATE_GATE);
> - if (IS_ERR(hw))
> - return PTR_ERR(hw);
> + ret = fsl_sai_clk_register(dev, base, &sai_clk->lock,
> + &sai_clk->bclk_div, &sai_clk->bclk_gate,
> + &sai_clk->bclk_hw, CSR_BCE_BIT, CR2_BCD,
> + data->offset + I2S_CR2, "BCLK");
> + if (ret)
> + return ret;
>
> return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
^^^
hw is removed above, and it's still here in this patch. It's removed in
the last patch. This will break git bisect.

Brian