Re: [PATCH 02/13] dt-bindings: clock: qcom,sm8550-dispcc: Add display CESTA support on SM8750

Dmitry Baryshkov
2026-04-20T17:46:02Z

On Mon, Apr 20, 2026 at 09:58:55PM +0530, Jagadeesh Kona wrote:
> On SM8750, a subset of DISPCC clocks is controlled by the display CESTA
> (Client State Aggregator) hardware. These clocks can be scaled to the
> desired frequency by sending votes to the display CRM(CESTA Resource
> manager) instead of programming DISPCC registers directly.
>
> Add bindings to allow the DISPCC node to reference the display CRM node
> for sending votes to CESTA hardware and the CRMC syscon regmap node
> which is used to read the frequency look up tables provided by CRM and
> populate this data in RCG's frequency tables for CESTA controlled clocks.
>
> Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
> ---
> .../bindings/clock/qcom,sm8550-dispcc.yaml | 48 ++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
> index 591ce91b8d54dd6f78a66d029882bcd94b53beda..3e049b2160a1781c866bb30b29f0da5c9e156b61 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
> @@ -60,6 +60,18 @@ properties:
> A phandle to an OPP node describing required MMCX performance point.
> maxItems: 1
>
> + qcom,crm:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the display CRM (CESTA Resource Manager) node, used to communicate
> + with the display CESTA (Client State Aggregator) hardware.

Is it going to be shared by several entities? If not, can be make a part
of the dispcc and get rid of the extra CC <-> CRM API?

> +
> + qcom,crmc-regmap:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the syscon providing the CRMC (CRM clock) regmap used
> + to read frequency LUTs (lookup tables) populated by the CRM.

Why is this coming as a syscon? Why isn't it just a register region of
the dispcc?

> +
> required:
> - compatible
> - clocks
> @@ -100,4 +112,40 @@ examples:
> power-domains = <&rpmhpd RPMHPD_MMCX>;
> required-opps = <&rpmhpd_opp_low_svs>;
> };
> +
> + - |
> + // Display clock controller node that controls some clocks
> + // using display CESTA(Client state Aggregator) hardware
> + #include <dt-bindings/clock/qcom,rpmh.h>
> + #include <dt-bindings/power/qcom,rpmhpd.h>
> +
> + clock-controller@af00000 {
> + compatible = "qcom,sm8750-dispcc";
> + reg = <0x0af00000 0x20000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&rpmhcc RPMH_CXO_CLK_A>,
> + <&gcc GCC_DISP_AHB_CLK>,
> + <&sleep_clk>,
> + <&dsi0_phy 0>,
> + <&dsi0_phy 1>,
> + <&dsi1_phy 0>,
> + <&dsi1_phy 1>,
> + <&dp0_phy 0>,
> + <&dp0_phy 1>,
> + <&dp1_phy 0>,
> + <&dp1_phy 1>,
> + <&dp2_phy 0>,
> + <&dp2_phy 1>,
> + <&dp3_phy 0>,
> + <&dp3_phy 1>;
> + power-domains = <&rpmhpd RPMHPD_MMCX>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> +
> + qcom,crm = <&disp_crm>;
> + qcom,crmc-regmap = <&disp_crmc>;
> +
> + #clock-cells = <1>;
> + #power-domain-cells = <1>;
> + #reset-cells = <1>;
> + };
> ...
>
> --
> 2.34.1
>

--
With best wishes
Dmitry