[PATCH 1/3] clk: qcom: lcc-msm8960: check regmap_read/regmap_write return values in probe

[Herman van Hazendonk <github.com@herrie.org>]

The PLL4 L-register read in probe was used to select between the 393 MHz
and 492 MHz frequency plans without checking whether the underlying
regmap operation succeeded; a silent failure would leave the rcg
structures pointing at whatever default they had at startup (the 393
MHz plan) and the chosen plan could be wrong for the running PLL,
producing incorrect audio clock rates without any diagnostic.

The unconditional write to register 0xc4 that arms the LPASS Primary
PLL mux on PLL4 had the same problem: a bus-level failure would leave
the mux at its default (PXO) and every downstream LCC clock would be
sourced from the wrong parent without a warning.

Use dev_err_probe() in both spots so the error is surfaced (and the
deferred-probe state machine handles the EPROBE_DEFER-from-bus-arbiter
case correctly) and the driver does not bind in a known-bad
configuration.

Signed-off-by: Herman van Hazendonk <github.com@herrie.org>
---
 drivers/clk/qcom/lcc-msm8960.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/lcc-msm8960.c b/drivers/clk/qcom/lcc-msm8960.c
index 7cba2ce3e408..44321c01f957 100644
--- a/drivers/clk/qcom/lcc-msm8960.c
+++ b/drivers/clk/qcom/lcc-msm8960.c
@@ -453,6 +453,7 @@ MODULE_DEVICE_TABLE(of, lcc_msm8960_match_table);
 static int lcc_msm8960_probe(struct platform_device *pdev)
 {
 	u32 val;
+	int ret;
 	struct regmap *regmap;
 
 	/* patch for the cxo <-> pxo difference */
@@ -468,7 +469,10 @@ static int lcc_msm8960_probe(struct platform_device *pdev)
 		return PTR_ERR(regmap);
 
 	/* Use the correct frequency plan depending on speed of PLL4 */
-	regmap_read(regmap, 0x4, &val);
+	ret = regmap_read(regmap, 0x4, &val);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret,
+				     "failed to read PLL4 L register\n");
 	if (val == 0x12) {
 		slimbus_src.freq_tbl = clk_tbl_aif_osr_492;
 		mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492;
@@ -479,7 +483,10 @@ static int lcc_msm8960_probe(struct platform_device *pdev)
 		pcm_src.freq_tbl = clk_tbl_pcm_492;
 	}
 	/* Enable PLL4 source on the LPASS Primary PLL Mux */
-	regmap_write(regmap, 0xc4, 0x1);
+	ret = regmap_write(regmap, 0xc4, 0x1);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret,
+				     "failed to select PLL4 on LPASS Primary PLL Mux\n");
 
 	return qcom_cc_really_probe(&pdev->dev, &lcc_msm8960_desc, regmap);
 }
-- 
2.43.0