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Sun, 28 Jun 2026 12:59:30 -0700 (PDT) Received: from [192.168.0.2] ([197.250.51.120]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-493ae96c85fsm15133505e9.5.2026.06.28.12.59.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2026 12:59:29 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Date: Sun, 28 Jun 2026 22:58:58 +0300 Subject: [PATCH RFC v5 03/12] dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset bindings Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20260628-zx29clk-v5-3-79ff044e4192@gmail.com> References: <20260628-zx29clk-v5-0-79ff044e4192@gmail.com> In-Reply-To: <20260628-zx29clk-v5-0-79ff044e4192@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Brian Masney Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Stefan_D=C3=B6singer?= X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 The clock controller of the zx297520v3 Low Speed Peripherals is relatively clean. One register per device with gates, muxes and resets and for some devices a divider. There are even bits in the matrix controller to control propagation of clock lines down to LSP. The clocks are sorted by register address and I am convinced that the device list is complete. There are however a few more registers that are likely extra dividers for TDM and I2S devices Signed-off-by: Stefan Dösinger --- Patch changelog: v5: Rename from lspclk to lspcrm Remove matrixcrm from example v4: Order properties compatible->reg->clocks->clock->names->#cells --- .../bindings/clock/zte,zx297520v3-lspcrm.yaml | 96 ++++++++++++++++++++++ MAINTAINERS | 1 + include/dt-bindings/clock/zte,zx297520v3-clk.h | 37 +++++++++ include/dt-bindings/reset/zte,zx297520v3-reset.h | 19 +++++ 4 files changed, 153 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/zte,zx297520v3-lspcrm.yaml b/Documentation/devicetree/bindings/clock/zte,zx297520v3-lspcrm.yaml new file mode 100644 index 000000000000..c510129068de --- /dev/null +++ b/Documentation/devicetree/bindings/clock/zte,zx297520v3-lspcrm.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/zte,zx297520v3-lspcrm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE zx297520v3 SoC LSP clock and reset controller + +maintainers: + - Stefan Dösinger + +description: | + This clock and reset controller controls low speed peripherals on the board. + This is a relatively isolated subsystem containing UART, I2C, I2S and SPI + devices. The controller is responsible for bringing the devices out of reset + and enabling their clocks as needed. + + The controller receives its clock signal from the matrix controller and need + to be declared as clock inputs. + + All available clocks are defined as preprocessor macros in the + 'dt-bindings/clock/zte,zx297520v3-clk.h' header. Resets are defined in the + 'dt-bindings/reset/zte,zx297520v3-reset.h' header. + +properties: + compatible: + const: zte,zx297520v3-lspcrm + + reg: + maxItems: 1 + + clocks: + items: + - description: Main PLL divided by 5 output from matrixcrm (124.8 MHz) + - description: Main PLL divided by 4 output from matrixcrm (156 MHz) + - description: Main PLL divided by 6 output from matrixcrm (104 MHz) + - description: Main PLL divided by 8 output from matrixcrm (78 MHz) + - description: Main PLL divided by 12 output from matrixcrm (52 MHz) + - description: Main oscillator output from matrixcrm (26 MHz) + - description: Timer oscillator output from matrixcrm (32 KHz) + - description: LSP pclk output from matrixcrm (26 MHz) + - description: TDM wclk mux output from matrixcrm + - description: DPLL divided by 4 output from matrixcrm (122.88 MHz) + + clock-names: + items: + - const: mpll_d5 + - const: mpll_d4 + - const: mpll_d6 + - const: mpll_d8 + - const: mpll_d12 + - const: osc26m + - const: osc32k + - const: pclk + - const: tdm_wclk + - const: dpll_d4 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + clock-controller@1400000 { + compatible = "zte,zx297520v3-lspcrm"; + reg = <0x01400000 0x100>; + clocks = <&matrixcrm ZX297520V3_LSP_MPLL_D5_WCLK>, + <&matrixcrm ZX297520V3_LSP_MPLL_D4_WCLK>, + <&matrixcrm ZX297520V3_LSP_MPLL_D6_WCLK>, + <&matrixcrm ZX297520V3_LSP_MPLL_D8_WCLK>, + <&matrixcrm ZX297520V3_LSP_MPLL_D12_WCLK>, + <&matrixcrm ZX297520V3_LSP_OSC26M_WCLK>, + <&matrixcrm ZX297520V3_LSP_OSC32K_WCLK>, + <&matrixcrm ZX297520V3_LSP_PCLK>, + <&matrixcrm ZX297520V3_LSP_TDM_WCLK>, + <&matrixcrm ZX297520V3_LSP_DPLL_D4_WCLK>; + clock-names = "mpll_d5", "mpll_d4", "mpll_d6", "mpll_d8", "mpll_d12", + "osc26m", "osc32k", "pclk", "tdm_wclk", "dpll_d4"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 0f9e588e4839..ee585982b859 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3867,6 +3867,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Odd fixes F: Documentation/arch/arm/zte/ F: Documentation/devicetree/bindings/arm/zte.yaml +F: Documentation/devicetree/bindings/clock/zte,zx297520v3-lspcrm.yaml F: Documentation/devicetree/bindings/soc/zte/ F: arch/arm/boot/dts/zte/ F: arch/arm/mach-zte/ diff --git a/include/dt-bindings/clock/zte,zx297520v3-clk.h b/include/dt-bindings/clock/zte,zx297520v3-clk.h index 8a6aa456a708..3c390211f897 100644 --- a/include/dt-bindings/clock/zte,zx297520v3-clk.h +++ b/include/dt-bindings/clock/zte,zx297520v3-clk.h @@ -131,4 +131,41 @@ #define ZX297520V3_SRAM0_PCLK 35 #define ZX297520V3_GSM_CFG_PCLK 36 +#define ZX297520V3_TIMER_L1_WCLK 1 +#define ZX297520V3_TIMER_L1_PCLK 2 +#define ZX297520V3_WDT_L2_WCLK 3 +#define ZX297520V3_WDT_L2_PCLK 4 +#define ZX297520V3_WDT_L3_WCLK 5 +#define ZX297520V3_WDT_L3_PCLK 6 +#define ZX297520V3_PWM_WCLK 7 +#define ZX297520V3_PWM_PCLK 8 +#define ZX297520V3_I2S0_WCLK 9 +#define ZX297520V3_I2S0_PCLK 10 +#define ZX297520V3_I2S1_WCLK 11 +#define ZX297520V3_I2S1_PCLK 12 +#define ZX297520V3_QSPI_WCLK 13 +#define ZX297520V3_QSPI_PCLK 14 +#define ZX297520V3_UART1_WCLK 15 +#define ZX297520V3_UART1_PCLK 16 +#define ZX297520V3_I2C1_WCLK 17 +#define ZX297520V3_I2C1_PCLK 18 +#define ZX297520V3_SPI0_WCLK 19 +#define ZX297520V3_SPI0_PCLK 20 +#define ZX297520V3_TIMER_LB_WCLK 21 +#define ZX297520V3_TIMER_LB_PCLK 22 +#define ZX297520V3_TIMER_LC_WCLK 23 +#define ZX297520V3_TIMER_LC_PCLK 24 +#define ZX297520V3_UART2_WCLK 25 +#define ZX297520V3_UART2_PCLK 26 +#define ZX297520V3_WDT_LE_WCLK 27 +#define ZX297520V3_WDT_LE_PCLK 28 +#define ZX297520V3_TIMER_LF_WCLK 29 +#define ZX297520V3_TIMER_LF_PCLK 30 +#define ZX297520V3_SPI1_WCLK 31 +#define ZX297520V3_SPI1_PCLK 32 +#define ZX297520V3_TIMER_L11_WCLK 33 +#define ZX297520V3_TIMER_L11_PCLK 34 +#define ZX297520V3_TDM_WCLK 35 +#define ZX297520V3_TDM_PCLK 36 + #endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */ diff --git a/include/dt-bindings/reset/zte,zx297520v3-reset.h b/include/dt-bindings/reset/zte,zx297520v3-reset.h index 81ffc8bc34c5..85a2f0707cdc 100644 --- a/include/dt-bindings/reset/zte,zx297520v3-reset.h +++ b/include/dt-bindings/reset/zte,zx297520v3-reset.h @@ -39,4 +39,23 @@ #define ZX297520V3_GMAC_RESET 7 #define ZX297520V3_VOU_RESET 8 +#define ZX297520V3_TIMER_L1_RESET 0 +#define ZX297520V3_WDT_L2_RESET 1 +#define ZX297520V3_WDT_L3_RESET 2 +#define ZX297520V3_PWM_RESET 3 +#define ZX297520V3_I2S0_RESET 4 +#define ZX297520V3_I2S1_RESET 5 +#define ZX297520V3_QSPI_RESET 6 +#define ZX297520V3_UART1_RESET 7 +#define ZX297520V3_I2C1_RESET 8 +#define ZX297520V3_SPI0_RESET 9 +#define ZX297520V3_TIMER_LB_RESET 10 +#define ZX297520V3_TIMER_LC_RESET 11 +#define ZX297520V3_UART2_RESET 12 +#define ZX297520V3_WDT_LE_RESET 13 +#define ZX297520V3_TIMER_LF_RESET 14 +#define ZX297520V3_SPI1_RESET 15 +#define ZX297520V3_TIMER_L11_RESET 16 +#define ZX297520V3_TDM_RESET 17 + #endif /* __DT_BINDINGS_RESET_ZX297520V3_H */ -- 2.53.0