Linux clock framework development
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From: Christian Marangi <ansuelsmth@gmail.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Brian Masney <bmasney@redhat.com>,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Christian Marangi <ansuelsmth@gmail.com>
Subject: [PATCH] clk: en7523: reset PCIE HB on init for AN7581
Date: Wed,  8 Jul 2026 10:40:44 +0200	[thread overview]
Message-ID: <20260708084045.8380-1-ansuelsmth@gmail.com> (raw)

It was reported that PCIE HB should be reset for AN7581 or some instability
or link training issue will be present on warm boot scenario.

Reset PCIE HB on clk HW init to handle warm boot problem with PCIe.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/clk/clk-en7523.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
index 1ab0e2eca5d3..c450d89bfa96 100644
--- a/drivers/clk/clk-en7523.c
+++ b/drivers/clk/clk-en7523.c
@@ -57,6 +57,7 @@
 
 #define REG_RST_CTRL2			0x830
 #define REG_RST_CTRL1			0x834
+#define   REG_PCIE_HB_RST		BIT(29)
 #define EN751221_REG_RST_DMT		0x84
 #define EN751221_REG_RST_USB		0xec
 
@@ -853,6 +854,12 @@ static int en7581_clk_hw_init(struct platform_device *pdev,
 	val = readl(base + REG_NP_SCU_PCIC);
 	writel(val | 3, base + REG_NP_SCU_PCIC);
 
+	val = readl(base + REG_RST_CTRL1);
+	val |= REG_PCIE_HB_RST;
+	writel(val, base + REG_RST_CTRL1);
+	val &= ~REG_PCIE_HB_RST;
+	writel(val, base + REG_RST_CTRL1);
+
 	return en7581_reset_register(&pdev->dev, base, en7581_rst_map,
 				     ARRAY_SIZE(en7581_rst_map),
 				     en7581_rst_ofs);
-- 
2.53.0


             reply	other threads:[~2026-07-08  8:41 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-08  8:40 Christian Marangi [this message]
2026-07-08 16:52 ` [PATCH] clk: en7523: reset PCIE HB on init for AN7581 Brian Masney
2026-07-09 13:48   ` Christian Marangi
2026-07-09 14:24     ` Brian Masney

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