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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38f03b0e976sm647015a91.5.2026.07.23.18.41.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2026 18:41:46 -0700 (PDT) From: Joey Lu To: mturquette@baylibre.com, sboyd@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Joey Lu , Alexandre Mergnat Subject: [PATCH v5 3/3] clk: nuvoton: ma35d1: fix ma35d1_clk_pll_determine_rate logic Date: Fri, 24 Jul 2026 09:40:39 +0800 Message-ID: <20260724014039.1239552-4-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724014039.1239552-1-a0987203069@gmail.com> References: <20260724014039.1239552-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit ma35d1_clk_pll_determine_rate() called ma35d1_pll_find_closest() unconditionally before the switch statement, and then every case branch overwrote pll_freq by reading the current hardware registers. For CAPLL and DDRPLL this means find_closest() ran unnecessarily (and incorrectly, since those PLLs are read-only) and its result was silently discarded. Fix by moving the find_closest() call inside the APLL/EPLL/VPLL branch where it belongs. Split CAPLL and DDRPLL into separate case labels mirroring ma35d1_clk_pll_recalc_rate(), with a shared req->rate = pll_freq tail after the switch and an explicit default label for unknown PLL IDs. Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock controller") Signed-off-by: Joey Lu Reviewed-by: Alexandre Mergnat --- drivers/clk/nuvoton/clk-ma35d1-pll.c | 31 ++++++++++++++-------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/clk/nuvoton/clk-ma35d1-pll.c b/drivers/clk/nuvoton/clk-ma35d1-pll.c index eb9d69d2077b..878b23bb5918 100644 --- a/drivers/clk/nuvoton/clk-ma35d1-pll.c +++ b/drivers/clk/nuvoton/clk-ma35d1-pll.c @@ -255,32 +255,33 @@ static int ma35d1_clk_pll_determine_rate(struct clk_hw *hw, if (req->best_parent_rate < PLL_FREF_MIN_FREQ || req->best_parent_rate > PLL_FREF_MAX_FREQ) return -EINVAL; - ret = ma35d1_pll_find_closest(pll, req->rate, req->best_parent_rate, - reg_ctl, &pll_freq); - if (ret < 0) - return ret; - switch (pll->id) { case CAPLL: + /* SMIC design: single control register */ reg_ctl[0] = readl_relaxed(pll->ctl0_base); pll_freq = ma35d1_calc_smic_pll_freq(reg_ctl[0], req->best_parent_rate); - req->rate = pll_freq; - - return 0; + break; case DDRPLL: - case APLL: - case EPLL: - case VPLL: + /* Standard design: read current rate, not configurable */ reg_ctl[0] = readl_relaxed(pll->ctl0_base); reg_ctl[1] = readl_relaxed(pll->ctl1_base); pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, req->best_parent_rate); - req->rate = pll_freq; - + break; + case APLL: + case EPLL: + case VPLL: + /* Configurable PLLs: find closest achievable rate */ + ret = ma35d1_pll_find_closest(pll, req->rate, req->best_parent_rate, + reg_ctl, &pll_freq); + if (ret < 0) + return ret; + break; + default: + req->rate = 0; return 0; } - req->rate = 0; - + req->rate = pll_freq; return 0; } -- 2.43.0