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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.18.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:18:11 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 10/32] clk: mediatek: Add PLL support to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:37 +0900 Message-ID: <20260803141659.559129-11-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Extend __mtk_clk_simple_probe() and __mtk_clk_simple_remove() to support PLLs. This reduces boilerplate code in apmixedsys drivers. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mtk.c | 19 ++++++++++++++++--- drivers/clk/mediatek/clk-mtk.h | 3 +++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 8148c21e6099..c3369a04cdec 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -20,6 +20,7 @@ #include "clk-gate.h" #include "clk-mux.h" #include "clk-cpumux.h" +#include "clk-pll.h" const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 }; EXPORT_SYMBOL_GPL(cg_regs_dummy); @@ -486,7 +487,7 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev, } /* Composite and divider clocks needs us to pass iomem pointer */ - if (mcd->composite_clks || mcd->divider_clks) { + if (mcd->composite_clks || mcd->divider_clks || mcd->plls) { if (!mcd->shared_io) base = devm_platform_ioremap_resource(pdev, 0); else @@ -514,7 +515,7 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev, num_clks = mcd->num_clks + mcd->num_composite_clks; num_clks += mcd->num_fixed_clks + mcd->num_factor_clks; num_clks += mcd->num_mux_clks + mcd->num_divider_clks; - num_clks += mcd->num_cpumuxes; + num_clks += mcd->num_cpumuxes + mcd->num_plls; clk_data = mtk_alloc_clk_data(num_clks); if (!clk_data) { @@ -522,11 +523,18 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev, goto free_base; } + if (mcd->plls) { + r = mtk_clk_register_plls(&pdev->dev, mcd->plls, + mcd->num_plls, clk_data); + if (r) + goto free_data; + } + if (mcd->fixed_clks) { r = mtk_clk_register_fixed_clks(mcd->fixed_clks, mcd->num_fixed_clks, clk_data); if (r) - goto free_data; + goto unregister_plls; } if (mcd->factor_clks) { @@ -630,6 +638,9 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev, if (mcd->fixed_clks) mtk_clk_unregister_fixed_clks(mcd->fixed_clks, mcd->num_fixed_clks, clk_data); +unregister_plls: + if (mcd->plls) + mtk_clk_unregister_plls(mcd->plls, mcd->num_plls, clk_data); free_data: mtk_free_clk_data(clk_data); free_base: @@ -668,6 +679,8 @@ static void __mtk_clk_simple_remove(struct platform_device *pdev, if (mcd->fixed_clks) mtk_clk_unregister_fixed_clks(mcd->fixed_clks, mcd->num_fixed_clks, clk_data); + if (mcd->plls) + mtk_clk_unregister_plls(mcd->plls, mcd->num_plls, clk_data); mtk_free_clk_data(clk_data); } diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 02fab4b166f2..b6504b3e77ed 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -23,6 +23,7 @@ #define MTK_WAIT_HWV_DONE_US 30 struct platform_device; +struct mtk_pll_data; /* * We need the clock IDs to start from zero but to maintain devicetree @@ -254,6 +255,8 @@ struct mtk_clk_desc { size_t num_mux_clks; const struct mtk_composite *cpumuxes; size_t num_cpumuxes; + const struct mtk_pll_data *plls; + size_t num_plls; const struct mtk_clk_rst_desc *rst_desc; spinlock_t *clk_lock; bool shared_io; -- 2.55.0