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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.18.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:18:48 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 18/32] clk: mediatek: mt6797: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:45 +0900 Message-ID: <20260803141659.559129-19-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The MT6797 clock drivers can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Drop the CLK_OF_DECLARE_DRIVER early init for infracfg; the kernel's deferred probe mechanism ensures dependent drivers like cpufreq are initialized correctly. Since all MT6797 clock drivers can now be built as modules, change Kconfig setting to "tristate". Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/Kconfig | 2 +- drivers/clk/mediatek/clk-mt6797.c | 140 +++++------------------------- 2 files changed, 24 insertions(+), 118 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index b58656a7e8c3..f5460ce3ffba 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -342,7 +342,7 @@ config COMMON_CLK_MT6795_VENCSYS This driver supports MediaTek MT6795 vencsys clocks. config COMMON_CLK_MT6797 - bool "Clock driver for MediaTek MT6797" + tristate "Clock driver for MediaTek MT6797" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK && ARM64 diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c index ebf850ac57f5..1934420375e8 100644 --- a/drivers/clk/mediatek/clk-mt6797.c +++ b/drivers/clk/mediatek/clk-mt6797.c @@ -379,29 +379,13 @@ static const struct mtk_composite top_muxes[] = { 0x0104, 1, 2), }; -static int mtk_topckgen_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - void __iomem *base; - struct device_node *node = pdev->dev.of_node; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data = mtk_alloc_clk_data(CLK_TOP_NR); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs), - clk_data); - - mtk_clk_register_composites(&pdev->dev, top_muxes, - ARRAY_SIZE(top_muxes), base, - &mt6797_clk_lock, clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} +static const struct mtk_clk_desc topckgen_desc = { + .factor_clks = top_fixed_divs, + .num_factor_clks = ARRAY_SIZE(top_fixed_divs), + .composite_clks = top_muxes, + .num_composite_clks = ARRAY_SIZE(top_muxes), + .clk_lock = &mt6797_clk_lock, +}; static const struct mtk_gate_regs infra0_cg_regs = { .set_ofs = 0x0080, @@ -539,58 +523,12 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = { FACTOR(CLK_INFRA_13M, "clk13m", "clk26m", 1, 2), }; -static struct clk_hw_onecell_data *infra_clk_data; - -static void mtk_infrasys_init_early(struct device_node *node) -{ - int r, i; - - if (!infra_clk_data) { - infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); - if (!infra_clk_data) - return; - - for (i = 0; i < CLK_INFRA_NR; i++) - infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); - } - - mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), - infra_clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - infra_clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} - -CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt6797-infracfg", - mtk_infrasys_init_early); - -static int mtk_infrasys_init(struct platform_device *pdev) -{ - int i; - struct device_node *node = pdev->dev.of_node; - - if (!infra_clk_data) { - infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); - if (!infra_clk_data) - return -ENOMEM; - } else { - for (i = 0; i < CLK_INFRA_NR; i++) { - if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER)) - infra_clk_data->hws[i] = ERR_PTR(-ENOENT); - } - } - - mtk_clk_register_gates(&pdev->dev, node, infra_clks, - ARRAY_SIZE(infra_clks), infra_clk_data); - mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), - infra_clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - infra_clk_data); -} +static const struct mtk_clk_desc infracfg_desc = { + .clks = infra_clks, + .num_clks = ARRAY_SIZE(infra_clks), + .factor_clks = infra_fixed_divs, + .num_factor_clks = ARRAY_SIZE(infra_fixed_divs), +}; #define MT6797_PLL_FMAX (3000UL * MHZ) @@ -646,68 +584,36 @@ static const struct mtk_pll_data plls[] = { 0x2B4, 4, 0x2BC, 0x2B8, 0), }; -static int mtk_apmixedsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} +static const struct mtk_clk_desc apmixedsys_desc = { + .plls = plls, + .num_plls = ARRAY_SIZE(plls), +}; static const struct of_device_id of_match_clk_mt6797[] = { { .compatible = "mediatek,mt6797-topckgen", - .data = mtk_topckgen_init, + .data = &topckgen_desc, }, { .compatible = "mediatek,mt6797-infracfg", - .data = mtk_infrasys_init, + .data = &infracfg_desc, }, { .compatible = "mediatek,mt6797-apmixedsys", - .data = mtk_apmixedsys_init, + .data = &apmixedsys_desc, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_match_clk_mt6797); -static int clk_mt6797_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init = of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r = clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt6797_drv = { - .probe = clk_mt6797_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt6797", .of_match_table = of_match_clk_mt6797, }, }; - -static int __init clk_mt6797_init(void) -{ - return platform_driver_register(&clk_mt6797_drv); -} - -arch_initcall(clk_mt6797_init); +module_platform_driver(clk_mt6797_drv); MODULE_DESCRIPTION("MediaTek MT6797 main clocks driver"); MODULE_LICENSE("GPL"); -- 2.55.0