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Wed, 05 Aug 2026 01:12:45 -0700 (PDT) From: Stanislaw Pal To: Jie Luo Cc: Bjorn Andersson , Stephen Boyd , Michael Turquette , Mieczyslaw Nalewaj , Brian Masney , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH] clk: qcom: ipq-cmn-pll: keep the CMN block bus clocks enabled Date: Wed, 5 Aug 2026 10:12:40 +0200 Message-ID: <20260805081240.11497-1-kuncy7@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <1dc44e5e-7787-47f7-938f-1ac0676d96d2@oss.qualcomm.com> References: <1dc44e5e-7787-47f7-938f-1ac0676d96d2@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On 8/5/2026 Jie Luo wrote: > Is there any use case that requires accessing the CMN PLL registers when > no downstream consumer is active? If not, I don't think a fix is needed > here. As you may have observed, debugfs clk_summary can still display > the clock rate correctly even when there is no downstream consumer and > the AHB and SYS clocks are disabled. The clk_summary observation does not show what it seems to show, and I have to correct my own previous mail on the same point: this driver does not set CLK_GET_RATE_NOCACHE, and clk_core_get_rate_recalc() only calls .recalc_rate for clocks that have that flag. So clk_summary (and clk_get_rate()) return the rate cached at registration time, when probe still held the bus clocks enabled - no register access happens at all. It displaying correct rates with the clocks gated is exactly the cached value; it says nothing about whether an actual access would survive. As for the use case: on IPQ5018 it is booting the SoC. With the clocks gated after probe, boards hang within milliseconds - 100% reproducible on some builds, before userspace exists, with no consumer anywhere - and the only variable that changes the outcome is holding this reference. That is also why I do not think moving runtime PM references into the clk ops would help this platform: by your own argument nothing calls the ops at that point, yet the SoC still dies. Whatever the fatal access is - a CCF path we have not pinned down, or something else in the same clock domain - the platform demonstrably does not survive the gate itself. One more general point: the CCF gives no guarantee that clk API calls only happen while some consumer device is runtime-active. The DT device link keeps the supplier active while the consumer *device* is active, but a consumer is free to call clk_set_rate()/clk_round_rate() at any time, including while itself runtime-suspended - and on IPQ5018 there is no link at all. So "registers are only accessed while a consumer is active" is not an invariant anything enforces; it just happens to hold on the platforms where the DT wiring exists. If there is an alternative fix you would prefer - a different clock handoff from the bootloader state, describing the in-silicon consumers in DT, anything else - I am happy to test it on this hardware. But as it stands, a mainline kernel cannot boot reliably on IPQ5018 without this change, which is why I believe a fix is needed and Cc'd stable. Thanks, Stanislaw