From: Conor Dooley <conor@kernel.org>
To: Changhuang Liang <changhuang.liang@starfivetech.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney@redhat.com>, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>,
Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@gmail.com>,
Alexey Charkov <alchark@gmail.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Keguang Zhang <keguang.zhang@gmail.com>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH v4 8/8] riscv: dts: starfive: jhb100: Add syscon nodes
Date: Mon, 10 Aug 2026 17:21:16 +0100 [thread overview]
Message-ID: <20260810-cattle-cloud-87676dc2b9d7@spud> (raw)
In-Reply-To: <20260809015054.210577-9-changhuang.liang@starfivetech.com>
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On Sat, Aug 08, 2026 at 06:50:54PM -0700, Changhuang Liang wrote:
> Add syscon nodes for JHB100 RISC-V BMC SoC. They contain
> pcieep0_ecsr_syscon | host0_syscon | husb0_syscon | husbd0_syscon |
> pcieep1_ecsr_syscon | host1_syscon | husb1_syscon | husbd1_syscon |
> gpu0_syscon | gpu1_syscon | husbcmn_syscon | b2h_syscon | h2b_syscon |
> vout_syscon | pcierp_ecsr_syscon | pcierp_syscon | usb_syscon |
> npu_syscon | per0_syscon | per1_syscon | per2_syscon | per3_syscon |
> sys0_syscon | sys1_syscon | sys2_syscon | strap_syscon |
> sfc0_filter_syscon | sfc1_filter_syscon | sfc2_filter_syscon.
>
> Also update the references of pll nodes.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
This looks okay to me. I'll expect to see it later squashed with the
initial support, as we discussed previously.
Cheers,
Conor.
> ---
> arch/riscv/boot/dts/starfive/jhb100.dtsi | 193 +++++++++++++++++++----
> 1 file changed, 159 insertions(+), 34 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
> index 6b2863fd3fd3..e76cf0f3c380 100644
> --- a/arch/riscv/boot/dts/starfive/jhb100.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
> @@ -282,36 +282,6 @@ pll1: clock-pll1 {
> clock-frequency = <1000000000>;
> };
>
> - pll2: clock-pll2 {
> - compatible = "fixed-clock";
> - #clock-cells = <0>;
> - clock-frequency = <903168000>;
> - };
> -
> - pll4: clock-pll4 {
> - compatible = "fixed-clock";
> - #clock-cells = <0>;
> - clock-frequency = <100700000>;
> - };
> -
> - pll5: clock-pll5 {
> - compatible = "fixed-clock";
> - #clock-cells = <0>;
> - clock-frequency = <100700000>;
> - };
> -
> - pll6: clock-pll6 {
> - compatible = "fixed-clock";
> - #clock-cells = <0>;
> - clock-frequency = <2400000000>;
> - };
> -
> - pll7: clock-pll7 {
> - compatible = "fixed-clock";
> - #clock-cells = <0>;
> - clock-frequency = <1950000000>;
> - };
> -
> per2_gmac2_rgmii_rx: clock-per2-gmac2-rgmii-rx {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -393,6 +363,97 @@ bus_nioc: bus {
> <0x4 0x00000000 0x4 0x00000000 0x2 0x0>;
> ranges;
>
> + pcieep0_ecsr_syscon: syscon@10511000 {
> + compatible = "starfive,jhb100-pcieep-ecsr-syscon", "syscon";
> + reg = <0x0 0x10511000 0x0 0x1000>;
> + };
> +
> + host0_syscon: syscon@10519000 {
> + compatible = "starfive,jhb100-host-syscon", "syscon";
> + reg = <0x0 0x10519000 0x0 0x1000>;
> + };
> +
> + husb0_syscon: syscon@10695000 {
> + compatible = "starfive,jhb100-husb-syscon", "syscon";
> + reg = <0x0 0x10695000 0x0 0x800>;
> + };
> +
> + husbd0_syscon: syscon@10695800 {
> + compatible = "starfive,jhb100-husbd-syscon", "syscon";
> + reg = <0x0 0x10695800 0x0 0x800>;
> + };
> +
> + gpu0_syscon: syscon@10745000 {
> + compatible = "starfive,jhb100-gpu-syscon", "syscon";
> + reg = <0x0 0x10745000 0x0 0x1000>;
> + };
> +
> + pcieep1_ecsr_syscon: syscon@10d11000 {
> + compatible = "starfive,jhb100-pcieep-ecsr-syscon", "syscon";
> + reg = <0x0 0x10d11000 0x0 0x1000>;
> + };
> +
> + host1_syscon: syscon@10d19000 {
> + compatible = "starfive,jhb100-host-syscon", "syscon";
> + reg = <0x0 0x10d19000 0x0 0x1000>;
> + };
> +
> + husb1_syscon: syscon@10e95000 {
> + compatible = "starfive,jhb100-husb-syscon", "syscon";
> + reg = <0x0 0x10e95000 0x0 0x800>;
> + };
> +
> + husbd1_syscon: syscon@10e95800 {
> + compatible = "starfive,jhb100-husbd-syscon", "syscon";
> + reg = <0x0 0x10e95800 0x0 0x800>;
> + };
> +
> + gpu1_syscon: syscon@10f45000 {
> + compatible = "starfive,jhb100-gpu-syscon", "syscon";
> + reg = <0x0 0x10f45000 0x0 0x1000>;
> + };
> +
> + husbcmn_syscon: syscon@11045000 {
> + compatible = "starfive,jhb100-husbcmn-syscon", "syscon";
> + reg = <0x0 0x11045000 0x0 0x1000>;
> + };
> +
> + b2h_syscon: syscon@11135000 {
> + compatible = "starfive,jhb100-b2h-syscon", "syscon";
> + reg = <0x0 0x11135000 0x0 0x400>;
> + };
> +
> + h2b_syscon: syscon@11135400 {
> + compatible = "starfive,jhb100-h2b-syscon", "syscon";
> + reg = <0x0 0x11135400 0x0 0x200>;
> + };
> +
> + vout_syscon: syscon@11135800 {
> + compatible = "starfive,jhb100-vout-syscon", "syscon";
> + reg = <0x0 0x11135800 0x0 0x400>;
> + };
> +
> + pcierp_ecsr_syscon: syscon@11711000 {
> + compatible = "starfive,jhb100-pcierp-ecsr-syscon", "syscon";
> + reg = <0x0 0x11711000 0x0 0x1000>;
> + };
> +
> + pcierp_syscon: syscon@11719000 {
> + compatible = "starfive,jhb100-pcierp-syscon", "syscon";
> + reg = <0x0 0x11719000 0x0 0x1000>;
> + #reset-cells = <1>;
> + };
> +
> + usb_syscon: syscon@11820000 {
> + compatible = "starfive,jhb100-usb-syscon", "syscon";
> + reg = <0x0 0x11820000 0x0 0x10000>;
> + };
> +
> + npu_syscon: syscon@118e5000 {
> + compatible = "starfive,jhb100-npu-syscon", "syscon";
> + reg = <0x0 0x118e5000 0x0 0x100>;
> + };
> +
> uart6: serial@11982000 {
> compatible = "starfive,jhb100-uart", "snps,dw-apb-uart";
> reg = <0x0 0x11982000 0x0 0x400>;
> @@ -410,7 +471,8 @@ uart6: serial@11982000 {
> per0crg: clock-controller@11a08000 {
> compatible = "starfive,jhb100-per0crg";
> reg = <0x0 0x11a08000 0x0 0x1000>;
> - clocks = <&osc>, <&pll6>,
> + clocks = <&osc>,
> + <&per0_syscon JHB100_PER0PLL_PLL6_OUT>,
> <&sys0crg JHB100_SYS0CLK_BMCPER0_CFG_400>,
> <&sys0crg JHB100_SYS0CLK_BMCPER0_CFG_800>,
> <&sys0crg JHB100_SYS0CLK_BMCPER0_NCNOC_INIT>,
> @@ -422,10 +484,17 @@ per0crg: clock-controller@11a08000 {
> #reset-cells = <1>;
> };
>
> + per0_syscon: syscon@11a09000 {
> + compatible = "starfive,jhb100-per0-syscon", "syscon";
> + reg = <0x0 0x11a09000 0x0 0x1000>;
> + clocks = <&osc>;
> + #clock-cells = <1>;
> + };
> +
> per1crg: clock-controller@11b40000 {
> compatible = "starfive,jhb100-per1crg";
> reg = <0x0 0x11b40000 0x0 0x1000>;
> - clocks = <&pll7>,
> + clocks = <&per1_syscon JHB100_PER1PLL_PLL7_OUT>,
> <&sys0crg JHB100_SYS0CLK_BMCPER1_NCNOC_INIT>,
> <&sys0crg JHB100_SYS0CLK_BMCPER1_CFG_800>,
> <&sys2crg JHB100_SYS2CLK_BMCPER1_NCNOC_TARG>,
> @@ -437,6 +506,13 @@ per1crg: clock-controller@11b40000 {
> #reset-cells = <1>;
> };
>
> + per1_syscon: syscon@11b41000 {
> + compatible = "starfive,jhb100-per1-syscon", "syscon";
> + reg = <0x0 0x11b41000 0x0 0x1000>;
> + clocks = <&osc>;
> + #clock-cells = <1>;
> + };
> +
> per2crg: clock-controller@11bc0000 {
> compatible = "starfive,jhb100-per2crg";
> reg = <0x0 0x11bc0000 0x0 0x1000>;
> @@ -458,6 +534,11 @@ per2crg: clock-controller@11bc0000 {
> #reset-cells = <1>;
> };
>
> + per2_syscon: syscon@11bc1000 {
> + compatible = "starfive,jhb100-per2-syscon", "syscon";
> + reg = <0x0 0x11bc1000 0x0 0x1000>;
> + };
> +
> per3crg: clock-controller@11c40000 {
> compatible = "starfive,jhb100-per3crg";
> reg = <0x0 0x11c40000 0x0 0x1000>;
> @@ -477,11 +558,16 @@ per3crg: clock-controller@11c40000 {
> #reset-cells = <1>;
> };
>
> + per3_syscon: syscon@11c41000 {
> + compatible = "starfive,jhb100-per3-syscon", "syscon";
> + reg = <0x0 0x11c41000 0x0 0x1000>;
> + };
> +
> sys0crg: clock-controller@13000000 {
> compatible = "starfive,jhb100-sys0crg";
> reg = <0x0 0x13000000 0x0 0x4000>;
> clocks = <&osc>, <&pll0>, <&pll1>,
> - <&pll2>;
> + <&sys0_syscon JHB100_SYS0PLL_PLL2_OUT>;
> clock-names = "osc", "pll0", "pll1", "pll2";
> #clock-cells = <1>;
> #reset-cells = <1>;
> @@ -491,7 +577,9 @@ sys1crg: clock-controller@13004000 {
> compatible = "starfive,jhb100-sys1crg";
> reg = <0x0 0x13004000 0x0 0x4000>;
> clocks = <&osc>, <&pll0>, <&pll1>,
> - <&pll2>, <&pll4>, <&pll5>,
> + <&sys0_syscon JHB100_SYS0PLL_PLL2_OUT>,
> + <&sys0_syscon JHB100_SYS0PLL_PLL4_OUT>,
> + <&sys0_syscon JHB100_SYS0PLL_PLL5_OUT>,
> <&sys0crg JHB100_SYS0CLK_NPU_NCNOC_INIT>;
> clock-names = "osc", "pll0", "pll1", "pll2",
> "pll4", "pll5", "npu_ncnoc_init";
> @@ -511,6 +599,28 @@ sys2crg: clock-controller@13008000 {
> #reset-cells = <1>;
> };
>
> + sys0_syscon: syscon@13010000 {
> + compatible = "starfive,jhb100-sys0-syscon", "syscon";
> + reg = <0x0 0x13010000 0x0 0x2000>;
> + clocks = <&osc>;
> + #clock-cells = <1>;
> + };
> +
> + sys1_syscon: syscon@13014000 {
> + compatible = "starfive,jhb100-sys1-syscon", "syscon";
> + reg = <0x0 0x13014000 0x0 0x4000>;
> + };
> +
> + sys2_syscon: syscon@13018000 {
> + compatible = "starfive,jhb100-sys2-syscon", "syscon";
> + reg = <0x0 0x13018000 0x0 0x2000>;
> + };
> +
> + strap_syscon: syscon@1301a000 {
> + compatible = "starfive,jhb100-strap-syscon", "syscon";
> + reg = <0x0 0x1301a000 0x0 0x2000>;
> + };
> +
> intc: interrupt-controller@13220000 {
> compatible = "starfive,jhb100-intc";
> reg = <0x0 0x13220000 0x0 0x80>;
> @@ -518,6 +628,21 @@ intc: interrupt-controller@13220000 {
> interrupt-controller;
> #interrupt-cells = <1>;
> };
> +
> + sfc0_filter_syscon: syscon@14090000 {
> + compatible = "starfive,jhb100-sfc-filter-syscon", "syscon";
> + reg = <0x0 0x14090000 0x0 0x1000>;
> + };
> +
> + sfc1_filter_syscon: syscon@14091000 {
> + compatible = "starfive,jhb100-sfc-filter-syscon", "syscon";
> + reg = <0x0 0x14091000 0x0 0x1000>;
> + };
> +
> + sfc2_filter_syscon: syscon@14092000 {
> + compatible = "starfive,jhb100-sfc-filter-syscon", "syscon";
> + reg = <0x0 0x14092000 0x0 0x1000>;
> + };
> };
> };
> };
> --
> 2.25.1
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prev parent reply other threads:[~2026-08-10 16:21 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-09 1:50 [PATCH v4 0/8] Add StarFive JHB100 syscon modules Changhuang Liang
2026-08-09 1:50 ` [PATCH v4 1/8] dt-bindings: soc: starfive: " Changhuang Liang
2026-08-09 1:50 ` [PATCH v4 2/8] clk: starfive: Add system-0 domain PLL clock driver Changhuang Liang
2026-08-10 16:22 ` Conor Dooley
2026-08-09 1:50 ` [PATCH v4 3/8] clk: starfive: Add peripheral-0 " Changhuang Liang
2026-08-09 1:50 ` [PATCH v4 4/8] clk: starfive: Add Peripheral-1 " Changhuang Liang
2026-08-09 1:50 ` [PATCH v4 5/8] reset: starfive: Introduce active_low Changhuang Liang
2026-08-10 16:22 ` Conor Dooley
2026-08-09 1:50 ` [PATCH v4 6/8] reset: starfive: Add syscon reset driver support Changhuang Liang
2026-08-09 1:50 ` [PATCH v4 7/8] soc: starfive: Add socinfo driver for JHB100 SoC Changhuang Liang
2026-08-10 16:05 ` Conor Dooley
2026-08-09 1:50 ` [PATCH v4 8/8] riscv: dts: starfive: jhb100: Add syscon nodes Changhuang Liang
2026-08-10 16:21 ` Conor Dooley [this message]
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