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Mon, 10 Aug 2026 00:03:20 -0700 (PDT) Received: from strix.doe.home ([197.250.226.68]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4800215078asm30548038f8f.12.2026.08.10.00.03.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Aug 2026 00:03:19 -0700 (PDT) From: =?UTF-8?q?Stefan=20D=C3=B6singer?= To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, bmasney@redhat.com, vkoul@kernel.org, neil.armstrong@linaro.org, linux@armlinux.org.uk, lee@kernel.org Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, mfd@lists.linux.dev Subject: [PATCH v10 12/12] ARM: dts: zte: Declare zx297520v3 CRM device nodes Date: Mon, 10 Aug 2026 10:03:10 +0300 Message-ID: <20260810070311.1110849-1-stefandoesinger@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260810-zx29clk-v10-0-63846490712c@gmail.com> References: <20260810-zx29clk-v10-0-63846490712c@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes use of the driver added in the previous patches. It wires up the uart clocks and resets and allows getting rid of the placeholder uartclk node. Signed-off-by: Stefan Dösinger --- Version 10: Fix issues with dt-check-style --mode=strict in newly added code, but left issues in existing nodes alone. Version 9: Sort new nodes by mmio address rename syscon-reboot to "reboot" adjust to changes in bindings Version 7: Add phy nodes to topcrm Remove syscon from matrixclk again Adapt remove now-removed extra clk inputs from matrix Add reset to LSP osc26m -> clock-26m for the fixed rate clocks, likewise for 32k Version 6: Add syscon to matrixclk Version 5: Re-name from *clk to *crm Add the syscon-reboot node here because the binding requires it Re-add accidentally dropped uart2 IRQ --- arch/arm/boot/dts/zte/zx297520v3.dtsi | 101 +++++++++++++++++++++++--- 1 file changed, 89 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/zte/zx297520v3.dtsi b/arch/arm/boot/dts/zte/zx297520v3.dtsi index a16c30a164bb..ebac3cd137df 100644 --- a/arch/arm/boot/dts/zte/zx297520v3.dtsi +++ b/arch/arm/boot/dts/zte/zx297520v3.dtsi @@ -3,12 +3,26 @@ * Copyright (c) 2026 Stefan Dösinger */ +#include #include +#include / { #address-cells = <1>; #size-cells = <1>; + osc26m: clock-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + osc32k: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -20,15 +34,6 @@ cpu@0 { }; }; - /* Base bus clock and default for the UART. It will be replaced once a clock driver has - * been added. - */ - uartclk: uartclk-26000000 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - timer { compatible = "arm,armv7-timer"; interrupts = , @@ -75,18 +80,87 @@ uart0: serial@131000 { arm,primecell-periphid = <0x0018c011>; reg = <0x00131000 0x1000>; interrupts = ; - clocks = <&uartclk>, <&uartclk>; + clocks = <&topcrm ZX297520V3_UART0_WCLK>, + <&topcrm ZX297520V3_UART0_PCLK>; clock-names = "uartclk", "apb_pclk"; + resets = <&topcrm ZX297520V3_UART0_RESET>; + status = "disabled"; }; + topcrm: clock-controller@13b000 { + compatible = "zte,zx297520v3-topcrm", "syscon"; + reg = <0x0013b000 0x400>; + #clock-cells = <1>; + clocks = <&osc26m>, <&osc32k>; + clock-names = "osc26m", "osc32k"; + interrupts = , + , + , + ; + interrupt-names = "usb-up", "usb-down", + "hsic-up", "hsic-down"; + #phy-cells = <1>; + #reset-cells = <1>; + + reboot { + compatible = "syscon-reboot"; + mask = <0x1>; + offset = <0x0>; + value = <0x1>; + }; + }; + + matrixcrm: clock-controller@1306000 { + compatible = "zte,zx297520v3-matrixcrm"; + reg = <0x01306000 0x400>; + #clock-cells = <1>; + clocks = <&osc26m>, <&osc32k>, + <&topcrm ZX297520V3_AHB_PCLK>, + <&topcrm ZX297520V3_MPLL>, + <&topcrm ZX297520V3_MPLL_D5>, + <&topcrm ZX297520V3_DPLL>, + <&topcrm ZX297520V3_GPLL>, + <&topcrm ZX297520V3_GPLL_D2>, + <&topcrm ZX297520V3_GATED_OSC26M>; + clock-names = "osc26m", "osc32k", "ahb", "mpll", + "mpll-d5", "dpll", "gpll", "gpll-d2", + "wclk-osc26m"; + #hwlock-cells = <1>; + #reset-cells = <1>; + }; + + lspcrm: clock-controller@1400000 { + compatible = "zte,zx297520v3-lspcrm"; + reg = <0x01400000 0x100>; + #clock-cells = <1>; + clocks = <&matrixcrm ZX297520V3_LSP_MPLL_D5_WCLK>, + <&matrixcrm ZX297520V3_LSP_MPLL_D4_WCLK>, + <&matrixcrm ZX297520V3_LSP_MPLL_D6_WCLK>, + <&matrixcrm ZX297520V3_LSP_MPLL_D8_WCLK>, + <&matrixcrm ZX297520V3_LSP_MPLL_D12_WCLK>, + <&matrixcrm ZX297520V3_LSP_OSC26M_WCLK>, + <&matrixcrm ZX297520V3_LSP_OSC32K_WCLK>, + <&matrixcrm ZX297520V3_LSP_PCLK>, + <&matrixcrm ZX297520V3_LSP_TDM_WCLK>, + <&matrixcrm ZX297520V3_LSP_DPLL_D4_WCLK>; + clock-names = "mpll-d5", "mpll-d4", "mpll-d6", + "mpll-d8", "mpll-d12", "osc26m", "osc32k", + "pclk", "tdm-wclk", "dpll-d4"; + #reset-cells = <1>; + resets = <&matrixcrm ZX297520V3_LSP_RESET>; + }; + uart1: serial@1408000 { compatible = "arm,pl011", "arm,primecell"; arm,primecell-periphid = <0x0018c011>; reg = <0x01408000 0x1000>; interrupts = ; - clocks = <&uartclk>, <&uartclk>; + clocks = <&lspcrm ZX297520V3_UART1_WCLK>, + <&lspcrm ZX297520V3_UART1_PCLK>; clock-names = "uartclk", "apb_pclk"; + resets = <&lspcrm ZX297520V3_UART1_RESET>; + status = "disabled"; }; @@ -95,8 +169,11 @@ uart2: serial@140d000 { arm,primecell-periphid = <0x0018c011>; reg = <0x0140d000 0x1000>; interrupts = ; - clocks = <&uartclk>, <&uartclk>; + clocks = <&lspcrm ZX297520V3_UART2_WCLK>, + <&lspcrm ZX297520V3_UART2_PCLK>; clock-names = "uartclk", "apb_pclk"; + resets = <&lspcrm ZX297520V3_UART2_RESET>; + status = "disabled"; }; }; -- 2.54.0