From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney@redhat.com>, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>
Cc: Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@gmail.com>,
Alexey Charkov <alchark@gmail.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Keguang Zhang <keguang.zhang@gmail.com>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Changhuang Liang <changhuang.liang@starfivetech.com>,
Hal Feng <hal.feng@starfivetech.com>
Subject: [PATCH v5 0/8] Add StarFive JHB100 syscon modules
Date: Fri, 28 Aug 2026 02:56:00 -0700 [thread overview]
Message-ID: <20260828095608.19955-1-changhuang.liang@starfivetech.com> (raw)
StarFive JHB100 has many syscon modules, as listed below:
- pcieep0_ecsr_syscon (PCIe endpoint 0 externel syscon)
- pcieep1_ecsr_syscon
- host0_syscon (Host0 syscon)
- host1_syscon
- husb0_syscon (Host USB 0 syscon)
- husb1_syscon
- husbd0_syscon (Host USB device 0 syscon)
- husbd1_syscon
- husbcmn_syscon (Host USB common syscon)
- gpu0_syscon (GPU0 syscon)
- gpu1_syscon
- b2h_syscon (BMC to Host syscon)
- h2b_syscon (Host to BMC syscon)
- vout_syscon (Video output syscon)
- pcierp_ecsr_syscon (PCIe root port externel syscon)
- pcierp_syscon (PCIe root port syscon)
- usb_syscon
- npu_syscon
- per0_syscon (Peripheral 0 syscon)
- per1_syscon
- per2_syscon
- per3_syscon
- sys0_syscon (System 0 syscon)
- sys1_syscon
- sys2_syscon
- strap_syscon
- sfc0_filter_syscon (SFC0 filter syscon)
- sfc1_filter_syscon
- sfc2_filter_syscon
Some syscon modules contain PLL, reset, and socinfo nodes
This series depends on the series:
https://lore.kernel.org/all/20260807112923.191627-1-changhuang.liang@starfivetech.com/
changes since v4:
PATCH 2:
- Constify name pointer
- flag ==> flags
- Use FIELD_GET() and FIELD_PREP()
- Use DEFINE_SHOW_ATTRIBUTE()
- Replace of_device_get_match_data() with device_get_match_data().
- Make the driver compatible with both MFD cell instantiation and
direct device tree node probing.
- select STARFIVE_JHB100_SOCINFO and select MFD_SYSCON
PATCH 3:
- The changes in PATCH 2 introduced a conflict with PATCH 3, requiring
modifications.
PATCH 7:
- Binds directly to the "starfive,jhb100-sys0-syscon" node.
- Instantiates the sys0 PLL clock driver as an MFD child cell,
since the syscon region contains both the revision register
and PLL controls.
- Uses devm_* APIs for automatic resource cleanup.
v4: https://lore.kernel.org/all/20260809015054.210577-1-changhuang.liang@starfivetech.com/
v3: https://lore.kernel.org/all/20260521012932.24163-1-changhuang.liang@starfivetech.com/
v2: https://lore.kernel.org/all/20260512083521.3448-1-changhuang.liang@starfivetech.com/
V1: https://lore.kernel.org/all/20260403054945.467700-1-changhuang.liang@starfivetech.com/
Changhuang Liang (8):
dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules
clk: starfive: Add system-0 domain PLL clock driver
clk: starfive: Add peripheral-0 domain PLL clock driver
clk: starfive: Add Peripheral-1 domain PLL clock driver
reset: starfive: Introduce active_low
reset: starfive: Add syscon reset driver support
soc: starfive: Add socinfo driver for JHB100 SoC
riscv: dts: starfive: jhb100: Add syscon nodes
.../soc/starfive/starfive,jhb100-syscon.yaml | 115 ++++
MAINTAINERS | 11 +
arch/riscv/boot/dts/starfive/jhb100.dtsi | 193 +++++-
drivers/clk/starfive/Kconfig | 10 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jhb100-pll.c | 593 ++++++++++++++++++
drivers/reset/starfive/Kconfig | 9 +
drivers/reset/starfive/Makefile | 1 +
.../reset/starfive/reset-starfive-common.c | 6 +-
.../reset/starfive/reset-starfive-common.h | 6 +
.../starfive/reset-starfive-jhb100-syscon.c | 62 ++
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/starfive/Kconfig | 6 +
drivers/soc/starfive/Makefile | 2 +
drivers/soc/starfive/socinfo/Kconfig | 13 +
drivers/soc/starfive/socinfo/Makefile | 2 +
drivers/soc/starfive/socinfo/jhb100-socinfo.c | 105 ++++
.../dt-bindings/clock/starfive,jhb100-crg.h | 12 +
.../dt-bindings/reset/starfive,jhb100-crg.h | 3 +
20 files changed, 1117 insertions(+), 35 deletions(-)
create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-pll.c
create mode 100644 drivers/reset/starfive/reset-starfive-jhb100-syscon.c
create mode 100644 drivers/soc/starfive/Kconfig
create mode 100644 drivers/soc/starfive/Makefile
create mode 100644 drivers/soc/starfive/socinfo/Kconfig
create mode 100644 drivers/soc/starfive/socinfo/Makefile
create mode 100644 drivers/soc/starfive/socinfo/jhb100-socinfo.c
--
2.25.1
next reply other threads:[~2026-08-28 13:29 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-28 9:56 Changhuang Liang [this message]
2026-08-28 9:56 ` [PATCH v5 1/8] dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 2/8] clk: starfive: Add system-0 domain PLL clock driver Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 3/8] clk: starfive: Add peripheral-0 " Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 4/8] clk: starfive: Add Peripheral-1 " Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 5/8] reset: starfive: Introduce active_low Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 6/8] reset: starfive: Add syscon reset driver support Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 7/8] soc: starfive: Add socinfo driver for JHB100 SoC Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 8/8] riscv: dts: starfive: jhb100: Add syscon nodes Changhuang Liang
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