From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 162B34189DE; Tue, 1 Sep 2026 07:26:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788247565; cv=none; b=LSZ1ytaekRgcWG93gk/yfddhUuZ/ClhwHKoDspZ8EmsjEjsSo/Oz4zelEqmzU61t0mcF95ra9UWyo7Ki8gdmuzfD9vC7p1I+TNzDMGXL7O8inASWsfD1go/9N8h3hVFRy760pSMcP6XDSozefAGgmW7oIK0kABOJ7FAgEWi/0rU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788247565; c=relaxed/simple; bh=e3GaSYAqCiCq9fK/ky1G9RqEHYDGDWsvKl/TBBHj+sU=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=oDAxJX6gtDCy5krdk3uoVJPIdfpgcIzHVnFKQHYHfee9gclF/NS46vaLOBvZ1AzgaPAXmkXv/pWFFMo/2yOM73PuKxfsMBcZ1Yqv9UP/3RODzE2E08gMXFjBDITeTqKyox0AFSQoJdXrtWaMxS13EKoTSS1IyabqtqA4q59tBIw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=G2XPwzg9; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="G2XPwzg9" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 6817OmDP21484579, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1788247489; bh=OKGtdySN4ADF+iTbgU5aXnNvD6a4rM1oYWK4YN0RUOw=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version: Content-Transfer-Encoding:Content-Type; b=G2XPwzg9pOQb3s7RHlLTYjJAPNJs5Q60hBMPKYQSwIUB7Yazky51ogCfCNoaDt4my gLI97zNVR+5qv2Lzw6nE4UVPXnAmykqitJRhUpuN/A9GRtU3TpWbfPZDHNE/Q5KyiA JxhzbNQU0PSg+EBskEygDt4+ys4Fn55cg1wdWloLjMkSVUyw46dsbMN1V7eg4IsnQv tyafxC6T/ROTaSXtdBA9dAIG9+8gyb/gU6bU0PBMNN3GG4pDDNgDAxvAAIIWsdEbok 6Vgg1ZbNMW9NGeLYUzafdjLxViIIlZi9IdWKGD8xyjDgR2egEpCgZcKMpV70wKCNM6 m/O50nxFxTtkQ== Received: from mail.realtek.com (rtkexhmbs03.realtek.com.tw[10.21.1.53]) by rtits2.realtek.com.tw (8.15.2/3.29/5.94) with ESMTPS id 6817OmDP21484579 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 1 Sep 2026 15:24:49 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS03.realtek.com.tw (10.21.1.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.43; Tue, 1 Sep 2026 15:24:47 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.2562.43 via Frontend Transport; Tue, 1 Sep 2026 15:24:46 +0800 From: Yu-Chun Lin To: , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v14 00/11] clk / reset: realtek: Add RTD1625 clock and reset support Date: Tue, 1 Sep 2026 15:24:35 +0800 Message-ID: <20260901072446.2563145-1-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Hello, This patch series adds the clock and reset controller support for Realtek's RTD1625 SoC platform. Because the reset controllers share the same register space with the clock controllers on this platform, we utilize the Auxiliary Bus framework to decouple them. The clock controllers act as the primary devices, registering the reset controllers as auxiliary devices. To make it easier for maintainers to review, the series has been organized by subsystem: 1. Device Tree Bindings: - Add bindings for the Realtek RTD1625 Clock & Reset Controllers. 2. Reset Subsystem: - Introduce the basic Realtek reset infrastructure. - Add the RTD1625 platform reset drivers. 3. Clock Subsystem Infrastructure: - Introduce a common probe, and add support for basic clocks including PLLs, gate clocks, mux clocks, and MMC-tuned PLLs. 4. Clock Platform Drivers: - Add the clock controller drivers for RTD1625-CRT and RTD1625-ISO. - These drivers provide the clock sources and instantiate the corresponding auxiliary reset devices. Best regards, Yu-Chun Lin --- Changes in v14: General: - Move Reviewed-by tags to the correct position. Patch 4: - Replace device_node_to_regmap() with devm_platform_ioremap_resource() and devm_regmap_init_mmio(). - Drop rtk_clk_remove(). Patch 8: - Replace and with to properly include DIV_ROUND_CLOSEST(). Patch 9 & 10: - Drop the .remove callbacks. v13: https://lore.kernel.org/lkml/20260812020009.3480538-1-eleanor.lin@realtek.com/ v12: https://lore.kernel.org/lkml/20260804163807.1285869-1-eleanor.lin@realtek.com/ v11: https://lore.kernel.org/lkml/20260728142806.1954638-1-eleanor.lin@realtek.com/ v10: https://lore.kernel.org/lkml/20260713155630.3054636-1-eleanor.lin@realtek.com/ v9: https://lore.kernel.org/lkml/20260624112940.3475605-1-eleanor.lin@realtek.com/ v8: https://lore.kernel.org/lkml/20260610080824.255063-1-eleanor.lin@realtek.com/ v7: https://lore.kernel.org/lkml/20260508111641.3192177-1-eleanor.lin@realtek.com/ v6: https://lore.kernel.org/lkml/20260402073957.2742459-1-eleanor.lin@realtek.com/ v5: https://lore.kernel.org/lkml/20260324025332.3416977-1-eleanor.lin@realtek.com/ v4: https://lore.kernel.org/lkml/20260313081100.596224-1-eleanor.lin@realtek.com/ v3: https://lore.kernel.org/lkml/20260122110857.12995-1-eleanor.lin@realtek.com/ v2: https://lore.kernel.org/lkml/20260113112333.821-1-eleanor.lin@realtek.com/ v1: https://lore.kernel.org/lkml/20251229075313.27254-1-eleanor.lin@realtek.com/ Cheng-Yu Lee (9): reset: Add Realtek basic reset support reset: realtek: Add RTD1625 reset controller driver clk: realtek: Introduce common probe() clk: realtek: Add support for phase locked loops (PLLs) clk: realtek: Add support for gate clock clk: realtek: Add support for mux clock clk: realtek: Add support for MMC-tuned PLL clocks clk: realtek: Add RTD1625-CRT clock controller driver clk: realtek: Add RTD1625-ISO clock controller driver Yu-Chun Lin (2): dt-bindings: clock: Add Realtek RTD1625 Clock & Reset Controller arm64: dts: realtek: Add clock support for RTD1625 .../bindings/clock/realtek,rtd1625-clk.yaml | 58 ++ MAINTAINERS | 10 + arch/arm64/boot/dts/realtek/kent.dtsi | 33 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/realtek/Kconfig | 48 ++ drivers/clk/realtek/Makefile | 12 + drivers/clk/realtek/clk-pll-mmc.c | 430 ++++++++++ drivers/clk/realtek/clk-pll.c | 217 +++++ drivers/clk/realtek/clk-pll.h | 60 ++ drivers/clk/realtek/clk-regmap-gate.c | 70 ++ drivers/clk/realtek/clk-regmap-gate.h | 65 ++ drivers/clk/realtek/clk-regmap-mux.c | 41 + drivers/clk/realtek/clk-regmap-mux.h | 43 + drivers/clk/realtek/clk-rtd1625-crt.c | 802 ++++++++++++++++++ drivers/clk/realtek/clk-rtd1625-iso.c | 141 +++ drivers/clk/realtek/clk-rtk-common.c | 82 ++ drivers/clk/realtek/clk-rtk-common.h | 37 + drivers/clk/realtek/freq_table.c | 57 ++ drivers/clk/realtek/freq_table.h | 22 + drivers/reset/Kconfig | 1 + drivers/reset/Makefile | 1 + drivers/reset/realtek/Kconfig | 19 + drivers/reset/realtek/Makefile | 3 + drivers/reset/realtek/reset-rtd1625.c | 262 ++++++ drivers/reset/realtek/reset-rtk-common.c | 73 ++ drivers/reset/realtek/reset-rtk-common.h | 29 + .../dt-bindings/clock/realtek,rtd1625-clk.h | 165 ++++ include/dt-bindings/reset/realtek,rtd1625.h | 171 ++++ 29 files changed, 2954 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/realtek,rtd1625-clk.yaml create mode 100644 drivers/clk/realtek/Kconfig create mode 100644 drivers/clk/realtek/Makefile create mode 100644 drivers/clk/realtek/clk-pll-mmc.c create mode 100644 drivers/clk/realtek/clk-pll.c create mode 100644 drivers/clk/realtek/clk-pll.h create mode 100644 drivers/clk/realtek/clk-regmap-gate.c create mode 100644 drivers/clk/realtek/clk-regmap-gate.h create mode 100644 drivers/clk/realtek/clk-regmap-mux.c create mode 100644 drivers/clk/realtek/clk-regmap-mux.h create mode 100644 drivers/clk/realtek/clk-rtd1625-crt.c create mode 100644 drivers/clk/realtek/clk-rtd1625-iso.c create mode 100644 drivers/clk/realtek/clk-rtk-common.c create mode 100644 drivers/clk/realtek/clk-rtk-common.h create mode 100644 drivers/clk/realtek/freq_table.c create mode 100644 drivers/clk/realtek/freq_table.h create mode 100644 drivers/reset/realtek/Kconfig create mode 100644 drivers/reset/realtek/Makefile create mode 100644 drivers/reset/realtek/reset-rtd1625.c create mode 100644 drivers/reset/realtek/reset-rtk-common.c create mode 100644 drivers/reset/realtek/reset-rtk-common.h create mode 100644 include/dt-bindings/clock/realtek,rtd1625-clk.h create mode 100644 include/dt-bindings/reset/realtek,rtd1625.h -- 2.43.0