Re: [PATCH v2 0/2] clk: ti: mux: resolve parent clocks by DT index, not by name

[Andreas Kemnade <andreas@kemnade.info>]

On Wed, 2 Sep 2026 11:15:56 +0200
Andreas Kemnade <andreas@kemnade.info> wrote:

> On Wed, 02 Sep 2026 10:30:02 +0200
> "Mathieu Dubois-Briand" <mathieu.dubois-briand@bootlin.com> wrote:
> 
> > On Wed Sep 2, 2026 at 8:26 AM CEST, Andreas Kemnade wrote:  
> > > Hi,
> > >
> > > this seems to produce on OMAP3 (DM3730), even with the init fix.
> > >
> > > [    0.000000] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff
> > > , max_idle_ns: 58327039986419 ns                                                
> > > [    0.000030] sched_clock: 32 bits at 33kHz, resolution 30517ns, wraps every 65
> > > 535999984741ns                                                                  
> > > [    0.013488] clk: failed to reparent gpt1_fck to omap_32k_fck: -22            
> > > [    0.019805] Failed to initialize '/ocp@68000000/target-module@48318000/timer@
> > > 0': -19                                                                         
> > >
> > > Regards,
> > > Andreas    
> > 
> > Hi Andreas,
> > 
> > That one will be a bit harder for me to debug, as I'm not sure I can
> > easily get this hardware. But looking at the device tree and the
> > reference manual, I suspect something is wrong in the omap3 device tree.
> > 
> > In omap3.dtsi, we have this node [1]:
> > 
> > &timer1_target {
> > 	ti,no-reset-on-init;
> > 	ti,no-idle;
> > 	timer@0 {
> > 		assigned-clocks = <&gpt1_fck>;
> > 		assigned-clock-parents = <&omap_32k_fck>;
> > 	};
> > };
> > 
> > I suspect that's the source of the error: __set_clk_parents() in
> > drivers/clk/clk-conf.c will try to set &omap_32k_fck as a parent of
> > &gpt1_fck. But looking at omap3xxx-clocks.dtsi [2], &omap_32k_fck is not
> > a valid parent:
> > 
> > 	gpt1_fck: gpt1_fck {
> > 		#clock-cells = <0>;
> > 		compatible = "ti,composite-clock";
> > 		clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
> > 	};
> >   
> the composite clock is meant to combine the two clocks into one,
> so you have one single clock with enable/disable functions and
> parents. At least that seems to be the idea.
> 
> If the system fully boots, you see:
> localhost:/sys/kernel/debug/clk/gpt1_fck# cat clk_possible_parents 
> omap_32k_fck sys_ck
>
after doing some hacks around gpt1, I could investigate a bit

We have:
localhost:/sys/kernel/debug/clk# grep '(' */clk_possible_parents 
clkout2_src_ck/clk_possible_parents:(missing) (missing) (missing) (missing)
gpt10_fck/clk_possible_parents:(missing) (missing)
gpt11_fck/clk_possible_parents:(missing) (missing)
gpt2_fck/clk_possible_parents:(missing) (missing)
gpt3_fck/clk_possible_parents:(missing) (missing)
gpt4_fck/clk_possible_parents:(missing) (missing)
gpt5_fck/clk_possible_parents:(missing) (missing)
gpt6_fck/clk_possible_parents:(missing) (missing)
gpt7_fck/clk_possible_parents:(missing) (missing)
gpt8_fck/clk_possible_parents:(missing) (missing)
gpt9_fck/clk_possible_parents:(missing) (missing)
mcbsp1_fck/clk_possible_parents:(missing) (missing)
mcbsp2_fck/clk_possible_parents:(missing) (missing)
mcbsp3_fck/clk_possible_parents:(missing) (missing)
mcbsp4_fck/clk_possible_parents:(missing) (missing)
mcbsp5_fck/clk_possible_parents:(missing) (missing)
sgx_fck/clk_possible_parents:(missing) (missing) (missing) (missing) (missing) (missing) (missing) (missing)
usim_fck/clk_possible_parents:(missing) (missing) (missing) (missing) (missing) (missing) (missing) (missing) (missing) (missing)
localhost:/sys/kernel/debug/clk# 

All these clocks are composite clocks.

so the early-registration of timer-ti-dm-systimer seems not to be
the main issue here. Looking around what might be affected,
mux clocks build into composite clocks:
:~/linux/arch/arm/boot/dts/ti/omap$ grep -l ti,composite-mux *.dts*
omap2420-clocks.dtsi
omap2430-clocks.dtsi
omap24xx-clocks.dtsi
omap36xx-am35xx-omap3430es2plus-clocks.dtsi
omap36xx-omap3430es2plus-clocks.dtsi
omap3xxx-clocks.dtsi
omap44xx-clocks.dtsi
omap54xx-clocks.dtsi

So havoc all over the place, just worst in omap3 because more critical
clocks are affected.

So I think we need either a revert of these patches or a some
kind of quirk in clk_hw_register_composite_pdata to pass throuch something
between the mux component and the composite.

Regrads,
Andreas