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Fri, 04 Sep 2026 04:10:06 -0700 (PDT) Received: from volcano9f6e-hostos.amd.com ([165.204.217.251]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33450e140d3sm2492230eec.4.2026.09.04.04.10.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 04:10:05 -0700 (PDT) From: Hemanth Selam To: Prashant Gaikwad , Stephen Boyd , Brian Masney , Jerome Brunet , Thierry Reding , Jonathan Hunter , Tero Kristo Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH] clk: tegra: fix typos in comments Date: Fri, 4 Sep 2026 16:39:57 +0530 Message-ID: <20260904110959.21527-1-hemanth.selam@gmail.com> X-Mailer: git-send-email 2.48.1 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Fix typos in comments, reported by scripts/checkpatch.pl using the misspelling list in scripts/spelling.txt. Only touches comments, no code changes. Assisted-by: Cursor:claude-opus-5 Signed-off-by: Hemanth Selam --- drivers/clk/tegra/clk.h | 2 +- include/linux/clk/ti.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 73efd2ff37c9..afa93ba505ab 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -255,7 +255,7 @@ struct tegra_clk_pll; * @set_gain: Callback to adjust N div for SDM enabled * PLL's based on fractional divider value. * @calc_rate: Callback used to change how out of table - * rates (dividers and multipler) are calculated. + * rates (dividers and multiplier) are calculated. * @adjust_vco: Callback to adjust the programming range of the * divider range (if SDM is present) * @set_defaults: Callback which will try to initialize PLL diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 54a3fa370004..61c4abf19995 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -51,7 +51,7 @@ struct clk_omap_reg { * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg * @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg - * @dcc_rate: rate atleast which DCC @dcc_mask must be set + * @dcc_rate: rate at least which DCC @dcc_mask must be set * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg -- 2.48.1