Linux clock framework development
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From: sashiko-bot@kernel.org
To: "Louis-Alexis Eyraud" <louisalexis.eyraud@collabora.com>
Cc: robh@kernel.org, linux-clk@vger.kernel.org, conor+dt@kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v6 27/27] clk: mediatek: Add MT8189 ufs clock support
Date: Fri, 04 Sep 2026 16:27:20 +0000	[thread overview]
Message-ID: <20260904162721.229C41F00A3D@smtp.kernel.org> (raw)
In-Reply-To: <20260904-mt8189-clocks-system-base-v6-27-5df247f56938@collabora.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Preexisting Use-After-Free risk when reset controller registration fails in `__mtk_clk_simple_probe`.
--

commit b8b3345488c1f0eb6db7c64bd2d428ce6c86087f
Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>

clk: mediatek: Add MT8189 ufs clock support
    
Add support for the MT8189 ufs clock controller, which provides clock gate 
control for Universal Flash Storage.

> diff --git a/drivers/clk/mediatek/clk-mt8189-ufs.c b/drivers/clk/mediatek/clk-mt8189-ufs.c
> new file mode 100644
> index 0000000000000..ec98fe01a5989
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8189-ufs.c

[ ... ]

> +static const struct mtk_clk_desc ufscfg_ao_reg_mcd = {
> +	.clks = ufscfg_ao_reg_clks,
> +	.num_clks = ARRAY_SIZE(ufscfg_ao_reg_clks),
> +	.rst_desc = &ufscfg_ao_rst_desc,
> +};

[ ... ]

> +static struct platform_driver clk_mt8189_ufs_drv = {
> +	.probe = mtk_clk_simple_probe,

[Severity: High]
This isn't a bug introduced by this patch, but does the inclusion of 
rst_desc expose a use-after-free risk in the Mediatek clock framework?

Looking at __mtk_clk_simple_probe() in drivers/clk/mediatek/clk-mtk.c, the 
framework registers the OF clock provider before the reset controller:

	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
	if (r)
		goto unregister_clks;

	if (mcd->rst_desc) {
		r = mtk_register_reset_controller_with_dev(&pdev->dev,
							   mcd->rst_desc);
		if (r)
			goto unregister_clks;
	}

If mtk_register_reset_controller_with_dev() fails, the error path jumps to 
unregister_clks and frees clk_data via mtk_free_clk_data(). 

Since it doesn't call of_clk_del_provider(node) during this teardown, does 
this leave a dangling pointer in the OF clock framework? Any subsequent OF 
clock lookup for this device would likely dereference the freed clk_data.

> +	.remove = mtk_clk_simple_remove,
> +	.driver = {
> +		.name = "clk-mt8189-ufs",
> +		.of_match_table = of_match_clk_mt8189_ufs,
> +	},
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com?part=27

  reply	other threads:[~2026-09-04 16:27 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-04 15:58 [PATCH v6 00/27] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 01/27] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8186 Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 02/27] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8192 Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 03/27] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8195 Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 04/27] dt-bindings: clock: mediatek: reorder MT8186 compatibles Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 05/27] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 06/27] dt-bindings: clock: mediatek: regroup MT8192 " Louis-Alexis Eyraud
2026-09-04 16:11   ` sashiko-bot
2026-09-04 15:58 ` [PATCH v6 07/27] dt-bindings: clock: mediatek: regroup MT8195 " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 08/27] dt-bindings: clock: mediatek: Add MT8189 system/base clocks and resets Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 09/27] clk: mediatek: Harmonize mtk_pll_fenc related symbol names Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 10/27] clk: mediatek: pll: Add BAR reset register offsets Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 11/27] clk: mediatek: pll: Factorise pll power on/off sequences Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 12/27] clk: mediatek: pll: Add PLL stabilization delay definition Louis-Alexis Eyraud
2026-09-04 16:11   ` sashiko-bot
2026-09-04 15:58 ` [PATCH v6 13/27] clk: mediatek: pll: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 14/27] clk: mediatek: pllfh: Add configurable clock ops to mtk_pllfh_data Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 15/27] clk: mediatek: pllfh: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 16/27] clk: mediatek: Move fhctl_parse_dt call into mtk_clk_register_pllfhs Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 17/27] clk: mediatek: pllfh: clear state data in mtk_clk_cleanup_pllfhs Louis-Alexis Eyraud
2026-09-04 16:18   ` sashiko-bot
2026-09-04 15:58 ` [PATCH v6 18/27] clk: mediatek: Add MT8189 apmixedsys clock support Louis-Alexis Eyraud
2026-09-04 16:17   ` sashiko-bot
2026-09-04 15:58 ` [PATCH v6 19/27] clk: mediatek: Add MT8189 topckgen " Louis-Alexis Eyraud
2026-09-04 16:20   ` sashiko-bot
2026-09-04 15:58 ` [PATCH v6 20/27] clk: mediatek: Add MT8189 vlpckgen " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 21/27] clk: mediatek: Add MT8189 vlpcfg " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 22/27] clk: mediatek: Add MT8189 bus " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 23/27] clk: mediatek: Add MT8189 dbgao " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 24/27] clk: mediatek: Add MT8189 dvfsrc " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 25/27] clk: mediatek: Add MT8189 i2c " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 26/27] clk: mediatek: Add MT8189 scp " Louis-Alexis Eyraud
2026-09-04 16:28   ` sashiko-bot
2026-09-04 15:58 ` [PATCH v6 27/27] clk: mediatek: Add MT8189 ufs " Louis-Alexis Eyraud
2026-09-04 16:27   ` sashiko-bot [this message]
2026-09-07 10:24 ` [PATCH v6 00/27] MT8189: Add support for system and base clock controllers AngeloGioacchino Del Regno

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