Re: [PATCH 4/5] clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] ADC1 and TSU module clocks are assigned to the wrong MSTOP register (BUS_PERI_VIDEO instead of BUS_MCPU2).
--

commit d7fdd574b02e4a749809136361e953c55d998f3c
Author: Biju Das <biju.das.jz@bp.renesas.com>

clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset

This commit adds the P20 clock, module clocks for ADC1 and TSU, and
their corresponding module resets for the RZ/G3S (R9A08G046) SoC.

> diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c
> --- a/drivers/clk/renesas/r9a08g046-cpg.c
> +++ b/drivers/clk/renesas/r9a08g046-cpg.c
[ ... ]
> @@ -559,6 +560,12 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
>  					MSTOP(BUS_MCPU2, BIT(0))),
>  	DEF_MOD("gpio_hclk",		R9A08G046_GPIO_HCLK, R9A08G046_OSCCLK, 0x598, 0,
>  					MSTOP(BUS_PERI_CPU, BIT(6))),
> +	DEF_MOD("adc1_adclk",		R9A08G046_ADC1_ADCLK, R9A08G046_CLK_P20, 0x5a8, 2,
> +					MSTOP(BUS_PERI_VIDEO, BIT(14))),
> +	DEF_MOD("adc1_pclk",		R9A08G046_ADC1_PCLK, R9A08G046_CLK_P20, 0x5a8, 3,
> +					MSTOP(BUS_PERI_VIDEO, BIT(14))),
> +	DEF_MOD("tsu_pclk",		R9A08G046_TSU_PCLK, R9A08G046_CLK_P20, 0x5ac, 0,
> +					MSTOP(BUS_PERI_VIDEO, BIT(15))),

[Severity: High]
Should these module clocks in r9a08g046_mod_clks be assigned to the MCU bus
(BUS_MCPU2) instead of the video bus (BUS_PERI_VIDEO)?

Writing to the video bus MSTOP register instead of the expected MCU bus
register will fail to enable the bus clocks for the ADC and TSU modules. When
the drivers attempt to probe and access their registers, the unclocked bus
can generate an asynchronous external abort, leading to a kernel panic.

>  	DEF_MOD("pci_aclk",		R9A08G046_PCI_ACLK, R9A08G046_CLK_P1, 0x608, 0,

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260911133653.115553-1-biju.das.jz@bp.renesas.com?part=4