Re: [PATCH v4 15/52] clk: qcom: gcc-eliza: Tie the CX power domain to controller

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Reset controller operations do not request runtime PM before accessing hardware registers, risking a bus error when the controller is suspended.
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commit 6eedff091b5ff334cffe34d7a6a6b3454bdf390d
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

clk: qcom: gcc-eliza: Tie the CX power domain to controller

This commit enables runtime PM for the GCC Eliza clock controller. By setting 
use_rpm to true, it allows the CX power domain to power down when all GCC 
consumers have released their clocks and GDSCs.

> diff --git a/drivers/clk/qcom/gcc-eliza.c b/drivers/clk/qcom/gcc-eliza.c
> index fe18942a59ac4..e26e6e6e52f10 100644
> --- a/drivers/clk/qcom/gcc-eliza.c
> +++ b/drivers/clk/qcom/gcc-eliza.c
> @@ -3068,6 +3068,7 @@ static const struct qcom_cc_desc gcc_eliza_desc = {
>  	.num_resets = ARRAY_SIZE(gcc_eliza_resets),
>  	.gdscs = gcc_eliza_gdscs,
>  	.num_gdscs = ARRAY_SIZE(gcc_eliza_gdscs),
> +	.use_rpm = true,

[Severity: High]
This is a pre-existing issue, but by setting use_rpm to true here, this
patch exposes it to the Eliza platform.

Reset controller operations in the Qualcomm clock subsystem do not appear to
request runtime PM before accessing hardware registers. If a consumer driver
asserts or deasserts a reset while its clocks are disabled, does
qcom_reset_set_assert() directly access the reset register while the GCC
device is powered off?

drivers/clk/qcom/reset.c:qcom_reset_set_assert() {
        ...
        regmap_update_bits(rst->regmap, map->reg, mask, assert ? mask : 0);
}

Since this patch allows the GCC clock controller and its CX power domain to
suspend, could this reset register access trigger a synchronous external
abort and lead to a kernel panic?

>  	.driver_data = &gcc_eliza_driver_data,
>  };
>

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260914-qcom-tie-cx-to-gcc-v4-0-9d5a606ada33@oss.qualcomm.com?part=15