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[5.184.233.93]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4871ff3a8easm3703919f8f.9.2026.09.18.05.05.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2026 05:05:22 -0700 (PDT) From: Stanislaw Pal To: Gabor Juhos , Bjorn Andersson , Stephen Boyd Cc: Brian Masney , Jerome Brunet , Konrad Dybcio , Abel Vesa , Varadarajan Narayanan , Gokul Sriram Palanisamy , Sricharan Ramabadhran , Mieczyslaw Nalewaj , Jie Luo , Georg Seema , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] clk: qcom: gcc-ipq5018: mark 'gpll0_main' clock as critical Date: Fri, 18 Sep 2026 14:05:20 +0200 Message-ID: <20260918120520.140553-1-kuncy7@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260918-ipq5018-mark-gpll0_main-critical-v1-1-fbe8f27a0106@gmail.com> References: <20260918-ipq5018-mark-gpll0_main-critical-v1-1-fbe8f27a0106@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Tested-by: Stanislaw Pal Tested on the TP-Link Archer AX55 v1, the board named in the commit message, on OpenWrt main with kernel 6.18.44 and ipq-cmn-pll built in. The image carries your patch and not the ipq-cmn-pll one, so this is your fix on its own: devm_pm_runtime_get_noresume() is absent from ipq_cmn_pll_clk_probe() and the CLK_IS_CRITICAL flag is the only change against main. The board boots reliably, with no hang and no watchdog reset. /sys/kernel/debug/clk/clk_summary shows the flag doing its work: gpll0_main sits at enable count 3 here, against 2 on an image that keeps the PLL alive through the ipq-cmn-pll reference instead. The chain you describe is visible on the hardware as well: gcc_cmn_blk_ahb_clk -> pcnoc_bfdcd_clk_src -> gpll0 -> gpll0_main Once the board is up, gpll0 has four other enabled consumers (USB, QPIC, MDIO, BLSP AHB) while the CPUs have already moved to a53pll. That matches the failure being confined to the probe window, when none of those exist yet and the CPUs still run off GPLL0. For what it is worth on the scope question: on this board the hang was reproducible with ipq-cmn-pll alone, which is what my patch addresses, but I agree the root cause is the one you are fixing here - any driver that takes and releases a clock early enough can pull the PLL out from under the CPUs. Happy to see it handled in gcc-ipq5018.