From: Long Zhao via B4 Relay <devnull+longzhao.ambarella.com@kernel.org>
To: Arnd Bergmann <arnd@arndb.de>,
Krzysztof Kozlowski <krzk@kernel.org>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org
Cc: "Long Zhao" <longzhao@ambarella.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Jerome Brunet" <jbrunet@baylibre.com>,
"Linus Walleij" <linusw@kernel.org>,
"Bartosz Golaszewski" <brgl@kernel.org>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Jiri Slaby" <jirislaby@kernel.org>,
"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
"Catalin Marinas" <catalin.marinas@arm.com>,
"Will Deacon" <will@kernel.org>, "Long Zhao" <zl020895@163.com>,
"Lee Jones" <lee@kernel.org>,
mfd@lists.linux.dev, devicetree@vger.kernel.org,
linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v8 11/18] gpio: pl061: use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH
Date: Mon, 21 Sep 2026 12:23:30 +0800 [thread overview]
Message-ID: <20260921-cv75-v5-v8-11-282ff5d98dda@ambarella.com> (raw)
In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com>
From: Long Zhao <longzhao@ambarella.com>
Use the standard IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH helpers
instead of open-coded edge and level comparisons.
Signed-off-by: Long Zhao <longzhao@ambarella.com>
---
drivers/gpio/gpio-pl061.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index 66aea0856bc4..2913daf46aff 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -167,9 +167,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
if (offset < 0 || offset >= PL061_GPIO_NR)
return -EINVAL;
- if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
- (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)))
- {
+ if ((trigger & IRQ_TYPE_LEVEL_MASK) && (trigger & IRQ_TYPE_EDGE_BOTH)) {
dev_err(gc->parent,
"trying to configure line %d for both level and edge "
"detection, choose one!\n",
@@ -184,7 +182,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
regmap_read(pl061->regmap, GPIOIS, &gpiois);
regmap_read(pl061->regmap, GPIOIBE, &gpioibe);
- if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
+ if (trigger & IRQ_TYPE_LEVEL_MASK) {
bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
/* Disable edge detection */
--
2.34.1
next prev parent reply other threads:[~2026-09-21 4:23 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-21 4:23 [PATCH v8 00/18] Ambarella CV75 SoC minimal bring-up Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 01/18] dt-bindings: arm: add Ambarella CV75 platforms Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 02/18] dt-bindings: mfd: syscon: add Ambarella CV75 secure scratchpad Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 03/18] dt-bindings: clock: add Ambarella CV75 RCT Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 04/18] dt-bindings: pinctrl: add Ambarella CV75 pinctrl Long Zhao via B4 Relay
2026-09-22 7:11 ` Linus Walleij
2026-09-22 8:28 ` zl020895
2026-10-01 7:03 ` Linus Walleij
2026-09-21 4:23 ` [PATCH v8 05/18] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 06/18] dt-bindings: serial: snps-dw-apb-uart: add ambarella,cv75-uart Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 07/18] clk: ambarella: add CV75 RCT clock controller Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 08/18] gpiolib: regmap: add write_data_after_dir quirk Long Zhao via B4 Relay
2026-09-22 7:17 ` Linus Walleij
2026-09-22 8:45 ` zl020895
2026-09-21 4:23 ` [PATCH v8 09/18] gpiolib: regmap: add gpio_regmap_get_chip() Long Zhao via B4 Relay
2026-09-21 10:35 ` Bartosz Golaszewski
2026-09-21 12:19 ` zl020895
2026-09-21 13:05 ` Bartosz Golaszewski
2026-09-21 4:23 ` [PATCH v8 10/18] gpio: pl061: convert register access to regmap Long Zhao via B4 Relay
2026-09-21 4:23 ` Long Zhao via B4 Relay [this message]
2026-09-22 7:24 ` [PATCH v8 11/18] gpio: pl061: use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH Linus Walleij
2026-09-21 4:23 ` [PATCH v8 12/18] gpio: pl061: use cleanup helpers for locks Long Zhao via B4 Relay
2026-09-22 7:24 ` Linus Walleij
2026-09-21 4:23 ` [PATCH v8 13/18] gpio: pl061: switch data path to gpio-regmap Long Zhao via B4 Relay
2026-09-22 7:25 ` Linus Walleij
2026-09-21 4:23 ` [PATCH v8 14/18] gpio: pl061: add Ambarella register-layout variant Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 15/18] pinctrl: ambarella: add CV75 pin controller Long Zhao via B4 Relay
2026-09-22 7:28 ` Linus Walleij
2026-10-01 7:05 ` Linus Walleij
2026-09-21 4:23 ` [PATCH v8 16/18] serial: 8250_dw: add Ambarella CV75 quirks Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 17/18] arm64: ambarella: add ARCH_AMBARELLA and CV75 EVK DT Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 18/18] MAINTAINERS: add ARM/AMBARELLA SoC support Long Zhao via B4 Relay
2026-09-21 10:31 ` [PATCH v8 00/18] Ambarella CV75 SoC minimal bring-up Bartosz Golaszewski
2026-09-21 11:08 ` zl020895
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