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Mon, 21 Sep 2026 03:25:34 -0700 (PDT) From: Akari Tsuyukusa To: Stephen Boyd , Brian Masney , Jerome Brunet , Matthias Brugger , AngeloGioacchino Del Regno Cc: Takashi Sakamoto , Danilo Krummrich , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Bjorn Helgaas , Akari Tsuyukusa , Nicolas Frattaroli , Chen-Yu Tsai , Laura Nao , Sjoerd Simons , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list:ARM/Mediatek SoC support), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support) Subject: [PATCH 2/6] clk: mediatek: Fix MT6797 clock onecell IDs Date: Mon, 21 Sep 2026 19:25:18 +0900 Message-ID: <20260921102522.1640072-3-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260921102522.1640072-1-akkun11.open@gmail.com> References: <20260921102522.1640072-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add the missing dummy clock at ID 0 to the MT6797 image, multimedia, VDEC and VENC clock providers. This keeps the descriptor-based onecell allocations consistent with the binding clock IDs and prevents out-of-bounds accesses. Assisted-by: GPT-5.6 Luna Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt6797-img.c | 1 + drivers/clk/mediatek/clk-mt6797-mm.c | 1 + drivers/clk/mediatek/clk-mt6797-vdec.c | 1 + drivers/clk/mediatek/clk-mt6797-venc.c | 1 + 4 files changed, 4 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt6797-img.c b/drivers/clk/mediatek/clk-mt6797-img.c index 338c69234f24..2a42ec0a4b14 100644 --- a/drivers/clk/mediatek/clk-mt6797-img.c +++ b/drivers/clk/mediatek/clk-mt6797-img.c @@ -20,6 +20,7 @@ static const struct mtk_gate_regs img_cg_regs = { GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate img_clks[] = { + GATE_DUMMY(CLK_DUMMY, "img_dummy"), GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_sel", 11), GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_sel", 10), GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_sel", 6), diff --git a/drivers/clk/mediatek/clk-mt6797-mm.c b/drivers/clk/mediatek/clk-mt6797-mm.c index ddb40b8a1a7d..d2349c1d2a55 100644 --- a/drivers/clk/mediatek/clk-mt6797-mm.c +++ b/drivers/clk/mediatek/clk-mt6797-mm.c @@ -30,6 +30,7 @@ static const struct mtk_gate_regs mm1_cg_regs = { GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate mm_clks[] = { + GATE_DUMMY(CLK_DUMMY, "mm_dummy"), GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0), GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1), GATE_MM0(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 2), diff --git a/drivers/clk/mediatek/clk-mt6797-vdec.c b/drivers/clk/mediatek/clk-mt6797-vdec.c index d832f48123f5..73339310fb51 100644 --- a/drivers/clk/mediatek/clk-mt6797-vdec.c +++ b/drivers/clk/mediatek/clk-mt6797-vdec.c @@ -31,6 +31,7 @@ static const struct mtk_gate_regs vdec1_cg_regs = { GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) static const struct mtk_gate vdec_clks[] = { + GATE_DUMMY(CLK_DUMMY, "vdec_dummy"), GATE_VDEC0(CLK_VDEC_CKEN_ENG, "vdec_cken_eng", "vdec_sel", 8), GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4), GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt6797-venc.c b/drivers/clk/mediatek/clk-mt6797-venc.c index fd4446f4a9d7..f616d61a0de4 100644 --- a/drivers/clk/mediatek/clk-mt6797-venc.c +++ b/drivers/clk/mediatek/clk-mt6797-venc.c @@ -22,6 +22,7 @@ static const struct mtk_gate_regs venc_cg_regs = { GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) static const struct mtk_gate venc_clks[] = { + GATE_DUMMY(CLK_DUMMY, "venc_dummy"), GATE_VENC(CLK_VENC_0, "venc_0", "mm_sel", 0), GATE_VENC(CLK_VENC_1, "venc_1", "venc_sel", 4), GATE_VENC(CLK_VENC_2, "venc_2", "venc_sel", 8), -- 2.55.0