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Mon, 21 Sep 2026 03:25:37 -0700 (PDT) From: Akari Tsuyukusa To: Stephen Boyd , Brian Masney , Jerome Brunet , Matthias Brugger , AngeloGioacchino Del Regno Cc: Takashi Sakamoto , Danilo Krummrich , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Bjorn Helgaas , Akari Tsuyukusa , Nicolas Frattaroli , Chen-Yu Tsai , Laura Nao , Sjoerd Simons , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list:ARM/Mediatek SoC support), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support) Subject: [PATCH 3/6] clk: mediatek: Reserve missing MT8167 clock ID Date: Mon, 21 Sep 2026 19:25:19 +0900 Message-ID: <20260921102522.1640072-4-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260921102522.1640072-1-akkun11.open@gmail.com> References: <20260921102522.1640072-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Reserve the binding-defined CLK_TOP_HDMTX_CLKDIG_CTS slot in the MT8167 top clock provider with a dummy clock. The clock is not implemented by the topckgen driver, but the slot must remain present in the onecell data to keep the descriptor allocation large enough for the registered IDs. Assisted-by: GPT-5.6 Luna Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8167.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-mt8167.c index c64d918c37de..c88c41aa7fdf 100644 --- a/drivers/clk/mediatek/clk-mt8167.c +++ b/drivers/clk/mediatek/clk-mt8167.c @@ -746,6 +746,7 @@ static const struct mtk_gate_regs top5_cg_regs = { GATE_MTK(_id, _name, _parent, &top5_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) static const struct mtk_gate top_clks[] = { + GATE_DUMMY(CLK_TOP_HDMTX_CLKDIG_CTS, "hdmtx_clkdig_cts_dummy"), /* TOP0 */ GATE_TOP0(CLK_TOP_PWM_MM, "pwm_mm", "pwm_mm_sel", 0), GATE_TOP0(CLK_TOP_CAM_MM, "cam_mm", "camtg_mm_sel", 1), -- 2.55.0