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Mon, 21 Sep 2026 03:25:43 -0700 (PDT) From: Akari Tsuyukusa To: Stephen Boyd , Brian Masney , Jerome Brunet , Matthias Brugger , AngeloGioacchino Del Regno Cc: Takashi Sakamoto , Danilo Krummrich , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Bjorn Helgaas , Akari Tsuyukusa , Nicolas Frattaroli , Chen-Yu Tsai , Laura Nao , Sjoerd Simons , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list:ARM/Mediatek SoC support), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support) Subject: [PATCH 5/6] clk: mediatek: Reserve missing MT8196 MDP clock IDs Date: Mon, 21 Sep 2026 19:25:21 +0900 Message-ID: <20260921102522.1640072-6-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260921102522.1640072-1-akkun11.open@gmail.com> References: <20260921102522.1640072-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Reserve the binding-defined CLK_MDP_SMI0_SMI and CLK_MDP1_SMI0_SMI IDs with dummy clocks in the MT8196 MDP clock providers. These clocks are not implemented by the current MDP clock driver and have no known consumers. Keeping the slots occupied preserves the binding-defined ID space and prevents out-of-bounds accesses in the descriptor-based onecell data. Assisted-by: GPT-5.6 Luna Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8196-mdpsys.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8196-mdpsys.c b/drivers/clk/mediatek/clk-mt8196-mdpsys.c index 7667d88f0eb0..2d8997d34201 100644 --- a/drivers/clk/mediatek/clk-mt8196-mdpsys.c +++ b/drivers/clk/mediatek/clk-mt8196-mdpsys.c @@ -66,6 +66,7 @@ static const struct mtk_gate mdp1_clks[] = { /* MDP1-0 */ GATE_MDP0(CLK_MDP1_MDP_MUTEX0, "mdp1_mdp_mutex0", "mdp", 0), GATE_MDP0(CLK_MDP1_SMI0, "mdp1_smi0", "mdp", 1), + GATE_DUMMY(CLK_MDP1_SMI0_SMI, "mdp1_smi0_smi_dummy"), GATE_MDP0(CLK_MDP1_APB_BUS, "mdp1_apb_bus", "mdp", 2), GATE_MDP0(CLK_MDP1_MDP_RDMA0, "mdp1_mdp_rdma0", "mdp", 3), GATE_MDP0(CLK_MDP1_MDP_RDMA1, "mdp1_mdp_rdma1", "mdp", 4), @@ -118,6 +119,7 @@ static const struct mtk_gate mdp_clks[] = { /* MDP0 */ GATE_MDP0(CLK_MDP_MDP_MUTEX0, "mdp_mdp_mutex0", "mdp", 0), GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0", "mdp", 1), + GATE_DUMMY(CLK_MDP_SMI0_SMI, "mdp_smi0_smi_dummy"), GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus", "mdp", 2), GATE_MDP0(CLK_MDP_MDP_RDMA0, "mdp_mdp_rdma0", "mdp", 3), GATE_MDP0(CLK_MDP_MDP_RDMA1, "mdp_mdp_rdma1", "mdp", 4), -- 2.55.0