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Mon, 21 Sep 2026 03:25:46 -0700 (PDT) From: Akari Tsuyukusa To: Stephen Boyd , Brian Masney , Jerome Brunet , Matthias Brugger , AngeloGioacchino Del Regno Cc: Takashi Sakamoto , Danilo Krummrich , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Bjorn Helgaas , Akari Tsuyukusa , Nicolas Frattaroli , Chen-Yu Tsai , Laura Nao , Sjoerd Simons , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list:ARM/Mediatek SoC support), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support) Subject: [PATCH 6/6] clk: mediatek: Reserve missing MT8516 top clock IDs Date: Mon, 21 Sep 2026 19:25:22 +0900 Message-ID: <20260921102522.1640072-7-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260921102522.1640072-1-akkun11.open@gmail.com> References: <20260921102522.1640072-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Reserve the binding-defined CLK_TOP_EMI_DDRPHY_SEL and CLK_TOP_DDRPHYCFG_SEL slots in the MT8516 top clock provider with dummy clocks. These muxes are not implemented by the Linux MT8516 clock driver, but their binding IDs must remain represented in the onecell data to preserve a valid ID-to-slot mapping. Assisted-by: GPT-5.6 Luna Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8516.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index 342a59019fea..b64674559878 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -545,6 +545,8 @@ static const struct mtk_gate_regs top5_cg_regs = { GATE_MTK(_id, _name, _parent, &top5_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate top_clks[] = { + GATE_DUMMY(CLK_TOP_EMI_DDRPHY_SEL, "emi_ddrphy_sel_dummy"), + GATE_DUMMY(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel_dummy"), /* TOP1 */ GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1), GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2), -- 2.55.0