Re: [PATCH v3 2/2] clk: qcom: Add support for camera clock controller on Maili

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] clk: qcom: missing frequency table update for cam_cc_cci_1_clk_src on Maili
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commit 9204e9b27b38229aa09fff0dc17f81cd19db9fc2
Author: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>

clk: qcom: Add support for camera clock controller on Maili

Maili camcc is mostly identical to Hawi camcc, with a few clocks
removed, frequency table updates for a few other clocks, and PLL
configuration changes. Hence, reuse the Hawi camera clock controller
driver and extend it for the Qualcomm Maili SoC.

> diff --git a/drivers/clk/qcom/camcc-hawi.c b/drivers/clk/qcom/camcc-hawi.c
> index aa52b99aec003..dc5c108ce608c 100644
> --- a/drivers/clk/qcom/camcc-hawi.c
> +++ b/drivers/clk/qcom/camcc-hawi.c

[ ... ]

> @@ -3106,12 +3105,35 @@ static const struct of_device_id cam_cc_hawi_match_table[] = {
>  
>  static int cam_cc_hawi_probe(struct platform_device *pdev)
>  {
> +	if (device_is_compatible(&pdev->dev, "qcom,maili-camcc")) {
> +		cam_cc_pll0.config = &cam_cc_pll0_config_maili;
> +		cam_cc_pll1.config = &cam_cc_pll1_config_maili;
> +		cam_cc_pll2.config = &cam_cc_pll2_config_maili;
> +		cam_cc_pll3.config = &cam_cc_pll3_config_maili;
> +		cam_cc_pll4.config = &cam_cc_pll4_config_maili;
> +		cam_cc_pll5.config = &cam_cc_pll5_config_maili;
> +		cam_cc_pll6.config = &cam_cc_pll6_config_maili;
> +		cam_cc_pll7.config = &cam_cc_pll7_config_maili;
> +		cam_cc_pll8.config = &cam_cc_pll8_config_maili;
> +
> +		cam_cc_camnoc_rt_axi_clk_src.freq_tbl = ftbl_cam_cc_camnoc_rt_axi_clk_src_maili;
> +		cam_cc_cci_0_clk_src.freq_tbl = ftbl_cam_cc_cci_0_clk_src_maili;
> +		cam_cc_ofe_clk_src.freq_tbl = ftbl_cam_cc_ofe_clk_src_maili;

[Severity: Medium]
Since cam_cc_cci_1_clk_src statically references ftbl_cam_cc_cci_0_clk_src,
should it also be updated to use the new Maili table here?

Without an update for cam_cc_cci_1_clk_src, it will continue using the old
Hawi frequency table (ftbl_cam_cc_cci_0_clk_src). This means cci_0 gets the
new P_CAM_CC_PLL0_OUT_EVEN with a /16 integer divider, while cci_1 remains
on P_CAM_CC_PLL0_OUT_ODD with a 3/32 fractional divider.

Could this mismatch and unintended configuration cause instability or failure
for cameras attached to the second Camera Control Interface (CCI_1) on the
Maili SoC?

> +
> +		cam_cc_hawi_clocks[CAM_CC_CCI_2_CLK_SRC] = NULL;
> +		cam_cc_hawi_clocks[CAM_CC_CCI_2_CLK] = NULL;
> +		cam_cc_hawi_clocks[CAM_CC_CSI5PHYTIMER_CLK_SRC] = NULL;
> +		cam_cc_hawi_clocks[CAM_CC_CSI5PHYTIMER_CLK] = NULL;
> +		cam_cc_hawi_clocks[CAM_CC_CSIPHY5_CLK] = NULL;
> +	}
> +
>  	return qcom_cc_probe(pdev, &cam_cc_hawi_desc);
>  }

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Sashiko AI review · https://sashiko.dev/#/patchset/20260921-maili_camcc-v3-0-2f8d739ac2d4@oss.qualcomm.com?part=2