From: sashiko-bot@kernel.org
To: "Pablo Mazzini" <pmazzini@gmail.com>
Cc: linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org
Subject: Re: [PATCH v1 02/11] clk: sunxi-ng: add Allwinner B288 CCU driver
Date: Wed, 23 Sep 2026 20:36:22 +0000 [thread overview]
Message-ID: <20260923203623.698291F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260923201701.43391-2-pmazzini@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] clk: sunxi-ng: shared gate conflict on csi bus clocks
--
commit ae2cfebe5340417fd7a0871fe9800b7e3353dc68
Author: Pablo Mazzini <pmazzini@gmail.com>
clk: sunxi-ng: add Allwinner B288 CCU driver
This commit introduces the clock control unit (CCU) driver for the Allwinner
B288 SoC, covering the PLLs, CPU/AHB/APB trees, module clocks, and bus
gates and resets.
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-b288.c b/drivers/clk/sunxi-ng/ccu-sun8i-b288.c
> new file mode 100644
> index 0000000000000..4c3ce02878d25
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-b288.c
[ ... ]
> +static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
> + 0x064, BIT(4), 0);
> +static SUNXI_CCU_GATE(bus_csi_s_clk, "bus-csi-s", "ahb1",
> + 0x064, BIT(8), 0);
> +static SUNXI_CCU_GATE(bus_csi_m_clk, "bus-csi-m", "ahb1",
> + 0x064, BIT(8), 0);
> +static SUNXI_CCU_GATE(bus_csi_misc_clk, "bus-csi-misc", "ahb1",
> + 0x064, BIT(8), 0);
> +static SUNXI_CCU_GATE(bus_adda_clk, "bus-adda", "apb1",
[Severity: High]
Does this create a shared gate conflict for the csi bus clocks?
These three distinct clock objects map to the exact same physical register
(0x064) and gate bit (BIT(8)). Because they are declared as separate clocks,
the Common Clock Framework tracks their reference counts independently.
If driver A enables the bus-csi-s clock and driver B enables the bus-csi-m
clock, the shared gate will be turned on. However, if driver A subsequently
disables bus-csi-s, the framework will clear the shared bit because the
bus-csi-s reference count reached zero.
Could this abruptly disable the active clock for driver B, potentially
causing hardware lockups, asynchronous external aborts, or device failure
during standard device probe, unbind, or runtime PM sequences?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260923201701.43391-1-pmazzini@gmail.com?part=2
next prev parent reply other threads:[~2026-09-23 20:36 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-23 20:16 [PATCH v1 01/11] dt-bindings: clock: add Allwinner B288 CCU Pablo Mazzini
2026-09-23 20:16 ` [PATCH v1 02/11] clk: sunxi-ng: add Allwinner B288 CCU driver Pablo Mazzini
2026-09-23 20:36 ` sashiko-bot [this message]
2026-09-24 9:03 ` [PATCH v1 01/11] dt-bindings: clock: add Allwinner B288 CCU Andre Przywara
2026-09-24 20:12 ` Pablo Mazzini
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