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Wed, 23 Sep 2026 12:21:42 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33e9684d643sm17609309eec.18.2026.09.23.12.21.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 12:21:41 -0700 (PDT) From: Taniya Das Subject: [PATCH v2 0/3] clk: qcom: Add Nord DPRX clock controller support Date: Thu, 24 Sep 2026 00:51:30 +0530 Message-Id: <20260924-nords_dprx-v2-0-fa4364e087ef@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIALomtGoC/03M3wrCIBTH8VcZ5zqHOsnqau8RI8w/TWi6PCWL4 btng6CbA58Dv+8KaJO3CKdmhWSzRx9DBd81oEcVbpZ4Uw2c8j090o6EmAxezJwWIqqNVFofBIM 6mJN1ftli56F69PiM6b21M/t+fxn5n8mMUGKE5Mp1jrIr6yNi+3ipu47T1NYDQynlA01Ofo+rA AAA X-Change-ID: 20260903-nords_dprx-4903d7acc841 To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Abel Vesa Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das , Abel Vesa X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIzMDA3NyBTYWx0ZWRfX0rVdgR6yVVIS 0jHCevE+m/XR12dZQzV9MMNpLwuGhRax9x2fmiHzhPL6zKz5bp06zWcxPXNQAhwbitWddVPnLPt wrHsRGekYNij7YcXJPPj9OsVoP5JYE0= X-Authority-Analysis: v=2.4 cv=R/6WitRX c=1 sm=1 tr=0 ts=6ab426c7 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=dhWb7Yg5Oiobcms0P14A:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-GUID: rvaMOnKANpScckmXNotXXiPxMZU7y176 X-Proofpoint-ORIG-GUID: rvaMOnKANpScckmXNotXXiPxMZU7y176 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIzMDA3NyBTYWx0ZWRfX7B91nwY0I5f7 46KF7OF+8FEfi3chNVgl39Anaopbiut5D5jB8ECOG4/aMdWrqw2WfQ1uPb3h6Tz4nTlDPpZPec5 vKiAzhI6cFrurmOgxW0Jf/WDU0jweeZqS5Ku6bQKRmfO7IrSA+n/nTIomLh4XMVo5iLkZ5Jn8A1 EL1Un/qK4FrjzN+v4aaBTcQQP23R+Zd07L6DhlV5pp6hc5uBGBwmgjDZ11oo7UeJM422XQl/WPU LxQQi6UwbUOL5VLrsnckmsLTCT7IfxRaJIOk5XwssQmPgm8IdqO8DNk4BP4KzsFY6eKxZtNUTQn X8SwQoOZDSxyxfFAfll7rkUEoPb3ozGnbNLViW/ZcNjkwkIQZJB30G1qo3WsN8d/V6LJznaPWOu 5OZl6VX+TUordairVSsJEInMEUN1NxH18s8209VNVuUHIme+aF9aM0jvnCx6CVZhQSkhQcmRfuJ DmS2GMgFFixim01r/2A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-23_06,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 malwarescore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 suspectscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609230077 Add support for the DisplayPort Receiver (DPRX) clock controllers found on Qualcomm Nord devices. There are two identical DPRX clock controller instances (DPRX0 and DPRX1), each providing clocks for the DPRX core, audio, AHB and video memory paths, along with their core PLLs. The DPRX PLLs are ZONDA_OLE instances whose PLL_ALPHA_VAL register has been widened to 28 bits to carry the fractional word at a finer resolution. The existing alpha-PLL core derives the ALPHA_VAL width solely from the register-map layout and can only express 16 or 40 bits, so the first patch adds an optional per-PLL alpha_width override that, when set, feeds the recalc_rate/round_rate scaling and the Zonda set_rate L-adjust MSB check. This is a prerequisite for the DPRX PLLs to lock to and report the correct rate. The series is organised as follows: - Patch 1 - alpha-PLL 28-bit ALPHA_VAL width. - Patch 2 - documents the Nord DPRX clock controller device tree bindings. - Patch 3 - adds the two DPRX clock controller drivers. Changes in v2: - Address review comments: remove unused definitions and includes, rewrap the alpha-width ternary, and clarify that DPRXCC provides clocks and resets. - Add RB-by tag [Abel] - Link to v1: https://lore.kernel.org/r/20260907-nords_dprx-v1-0-d472af3f01b1@oss.qualcomm.com Signed-off-by: Taniya Das --- Taniya Das (3): clk: qcom: clk-alpha-pll: support a 28-bit ALPHA_VAL width dt-bindings: clock: qcom: document the Nord DPRX Clock Controller clk: qcom: dprxcc: Add Nord DPRX clock controller support .../bindings/clock/qcom,nord-dprxcc.yaml | 68 ++++ drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-alpha-pll.c | 8 +- drivers/clk/qcom/clk-alpha-pll.h | 3 + drivers/clk/qcom/dprxcc0-nord.c | 434 +++++++++++++++++++++ drivers/clk/qcom/dprxcc1-nord.c | 433 ++++++++++++++++++++ include/dt-bindings/clock/qcom,nord-dprxcc.h | 27 ++ 8 files changed, 981 insertions(+), 4 deletions(-) --- base-commit: a8c591ed6b672915e0be57843f943a2a723aff40 change-id: 20260903-nords_dprx-4903d7acc841 Best regards, -- Taniya Das