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Wed, 23 Sep 2026 12:21:54 -0700 (PDT) X-Received: by 2002:a05:693c:87d8:b0:33e:bbcc:eb99 with SMTP id 5a478bee46e88-34001eff31fmr90647eec.18.1790191314050; Wed, 23 Sep 2026 12:21:54 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33e9684d643sm17609309eec.18.2026.09.23.12.21.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 12:21:53 -0700 (PDT) From: Taniya Das Date: Thu, 24 Sep 2026 00:51:32 +0530 Subject: [PATCH v2 2/3] dt-bindings: clock: qcom: document the Nord DPRX Clock Controller Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260924-nords_dprx-v2-2-fa4364e087ef@oss.qualcomm.com> References: <20260924-nords_dprx-v2-0-fa4364e087ef@oss.qualcomm.com> In-Reply-To: <20260924-nords_dprx-v2-0-fa4364e087ef@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Abel Vesa Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIzMDA3NyBTYWx0ZWRfX6AcGY8JGrQDA MoBKGCH7NmRS+n75hq2HQvuGaJj70zZxlehpO2hrJxs2RWlmsPwlREXNF1/0K3pYfmuKmZLbunP VCf1yUlVsCcT8JHU+YEQtdr+E//k6jY= X-Authority-Analysis: v=2.4 cv=R/6WitRX c=1 sm=1 tr=0 ts=6ab426d3 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=1x_EA7c-f_fbMv8ZdKgA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-GUID: 3creRARU7riFw53LfcHQWqeidsdaJpTu X-Proofpoint-ORIG-GUID: 3creRARU7riFw53LfcHQWqeidsdaJpTu X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIzMDA3NyBTYWx0ZWRfX52IltiIttgie Iyds+C29sr55lRKhri4orkvcqatZmdSHDm0GuvOVz/XX2502SqrRsCLDx9t5wqNrof83J/ahM2B DxxPmRVQe15MrYl+hpmOBGi3aQgkCF1nGGQ5AO8xDu/EeJXHkVXoNfU1S+GpVxrjJajLzyMypys pMMsYCWzTVg5e2hCsR/hlz/GSSMmNymeEsMsc135xIHi93UVm5C1Lzxcu3B8G3iSlihhHV4tkkz to/9k/Un3WTgr+U63KdMx5iNmbnxFAw5OT/BFVr9EsxryZ0UwsyMTCbeION4CXcB79STX2TxNpA arfRweXMV9Kio8M5hTGsUGAmmmJ+1/Rc5ttSWGQ5vHu+kWtZd3Ml7FSqVP/pmzNRxSwFOnHMwx3 M7yZkrKnDjmAJD3gkg+huCAtcCV9TOA/a9Wh/oEcRRnIrSc5gk1MHZBJQQsFCxv1ODSNeBHt4u3 XZG8v77nEbiFrTdgH+A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-23_06,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 malwarescore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 suspectscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609230077 Add bindings documentation for the Nord DisplayPort Receiver (DPRX) Clock Controller. Signed-off-by: Taniya Das --- .../bindings/clock/qcom,nord-dprxcc.yaml | 68 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,nord-dprxcc.h | 27 +++++++++ 2 files changed, 95 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,nord-dprxcc.yaml b/Documentation/devicetree/bindings/clock/qcom,nord-dprxcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..e3553e0eecd5027155b4dca5c0596e3140641aa9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,nord-dprxcc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,nord-dprxcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm DPRX Clock & Reset Controller on Nord + +maintainers: + - Taniya Das + +description: | + Qualcomm dprx clock control module provides the clocks, and resets + domains on Nord. + + See also: + include/dt-bindings/clock/qcom,nord-dprxcc.h + +properties: + compatible: + enum: + - qcom,nord-dprxcc0 + - qcom,nord-dprxcc1 + + clocks: + items: + - description: XO clock source + - description: DPRX CFG AHB clock from NWGCC + - description: Sleep clock source + + power-domains: + description: + MMCX power domain. + maxItems: 1 + + required-opps: + description: + MMCX performance point. + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + - required-opps + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + clock-controller@a940000 { + compatible = "qcom,nord-dprxcc0"; + reg = <0x0a940000 0xc000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&nwgcc NW_GCC_DPRX0_CFG_AHB_CLK>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,nord-dprxcc.h b/include/dt-bindings/clock/qcom,nord-dprxcc.h new file mode 100644 index 0000000000000000000000000000000000000000..62c26b58ebef04f05ea1dc77664c03aaad65baa4 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-dprxcc.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DPRX_CC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_DPRX_CC_NORD_H + +/* DPRX_CC clocks */ +#define DPRX_CC_AHB_CLK 0 +#define DPRX_CC_AUD_CLK 1 +#define DPRX_CC_AUDIO_CLK_SRC 2 +#define DPRX_CC_CORE_AHB_DIV_CLK_SRC 3 +#define DPRX_CC_CORE_AUD_DIV_CLK_SRC 4 +#define DPRX_CC_CORE_RCG0_CLK_SRC 5 +#define DPRX_CC_CORE_RCG2_CLK_SRC 6 +#define DPRX_CC_CORE_RCG3_CLK_SRC 7 +#define DPRX_CC_MDP_MEM_CLK 8 +#define DPRX_CC_MMCX_XO_CLK 9 +#define DPRX_CC_PLL0 10 +#define DPRX_CC_PLL1 11 +#define DPRX_CC_VID_MEM_CLK 12 + +/* DPRX_CC resets */ +#define DPRX_CC_DPRX_BLK_BCR 0 + +#endif -- 2.34.1